A method of forming high definition elements for electrical and electronic devices, substrates, and other components from or including viscous material. The method includes inverting the electrical components after the viscous material is applied and maintaining the inverted orientation until the viscous material dries or cures enough to maintain definition of its perimeter and edge characteristics.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor substrate including at least one laterally unconstrained adhesive patch comprised of a viscous adhesive material, the at least one adhesive patch including a first surface adjacent and supported from beneath by said semiconductor substrate and a second, smaller exposed surface opposite said first surface exhibiting a generally planar portion over a substantial portion thereof, said semiconductor substrate including said at least one adhesive patch formed by: providing a semiconductor substrate; dispensing a viscous adhesive material on said semiconductor substrate; and inverting said semiconductor substrate without effecting substantial lateral confinement of said adhesive material and maintaining said semiconductor substrate in an inverted position at least until said viscous adhesive material sufficiently stabilizes so as to exhibit a desired stable shape and a lateral boundary defining sizes of said first and second surfaces of said at least one adhesive patch and wherein at least a substantial portion of said second, smaller surface of said adhesive patch exhibits a generally planar configuration and said size of said second, smaller surface is smaller that said size of said first surface.
2. The semiconductor substrate of claim 1 , wherein dispensing said viscous adhesive material, comprises: placing a template, including at least one aperture, on said semiconductor substrate; depositing said adhesive material into said at least one aperture; and removing said template prior to substantially inverting said semiconductor substrate.
3. A flip-chip including at least one laterally unconstrained conductive bump comprised of a viscous conductive material, the at least one conductive bump exhibiting a height-to-width ratio of at least approximately 3 to 1 and including a first surface adjacent and supported from beneath by said flip-chip and a second exposed surface opposite said first surface, said flip chip including said at least one conductive bump formed by: providing said flip-chip with at least one bond pad; dispensing a viscous conductive material on said flip-chip to define at least one conductive bump of a selected configuration exhibiting a height-to-width ratio of at least approximately 3 to 1, said at least one conductive bump in electrical communication with said at least one bond pad of said flip-chip and including a first surface adjacent said flip-chip and a second surface opposite said first surface; and inverting said flip-chip without substantial lateral confinement of said viscous conductive material and maintaining said flip-chip in an inverted position at least until said conductive material substantially stabilizes so as to exhibit a desired stable shape and lateral boundary substantially defining sizes of said first and second surfaces of said at least one conductive.
4. The flip-chip of claim 3 , wherein dispensing said viscous conductive material includes: placing a template, including at least one aperture, on said flip-chip; depositing a conductive material into said template aperture; and removing said template prior to inverting said flip-chip.
5. The semiconductor substrate of claim 1 , wherein said viscous adhesive material of said at least one adhesive patch comprises at least one of the group consisting of a polyimide, a phenolic resin, a thermoplastic, and a thermosetting plastic.
6. The semiconductor substrate of claim 1 , wherein said at least one adhesive patch comprises at least one lateral edge exhibiting an angle of repose of approximately 20 degrees.
7. The semiconductor substrate of claim 1 , wherein said at least one adhesive patch comprises at least one trailing edge exhibiting an angle of repose of approximately 13 degrees.
8. The semiconductor substrate of claim 1 , wherein said at least one adhesive patch comprises at least one leading edge exhibiting an angle of repose of approximately 20 degrees.
9. The semiconductor substrate of claim 2 , wherein said template including at least one aperture comprises a print screen including a plurality of apertures.
10. The semiconductor substrate of claim 2 , wherein said template including at least one aperture comprises a stencil including a plurality of apertures.
11. The flip-chip of claim 3 , wherein said at least one conductive bump comprises at least one lateral edge exhibiting an angle of repose of approximately 20 degrees.
12. The flip-chip of claim 3 , wherein said at least one conductive bump comprises at least one trailing edge exhibiting an angle of repose of approximately 12 degrees.
13. The flip-chip of claim 3 , wherein said at least one conductive bump comprises at least one leading edge exhibiting an angle of repose of approximately 20 degrees.
14. The flip-chip of claim 3 , wherein said conductive material of said at least one conductive bump comprises a conductive polymer material.
15. The flip-chip of claim 3 , wherein said viscous conductive material of said at least one conductive bump comprises at least one of the group consisting of a polyimide, a phenolic resin, a thermoplastic, and a thermosetting plastic.
16. The flip-chip of claim 4 , wherein said template having at least one aperture comprises a print screen including a plurality of apertures.
17. The flip-chip of claim 4 , wherein said template having at least one aperture comprises a stencil including a plurality of apertures.
18. A semiconductor substrate including at least one laterally unconstrained adhesive patch comprised of a viscous adhesive material exhibiting a stable, self-supporting shape, the at least one adhesive patch including a first surface adjacent and supported from beneath by said semiconductor substrate and a second smaller, exposed surface opposite said first surface, said second smaller, exposed surface exhibiting a generally planar portion over a substantial portion thereof.
19. The semiconductor substrate of claim 18 , wherein said viscous adhesive material comprises at least one of the group consisting of a polyimide, a phenolic resin, a thermoplastic, and a thermosetting plastic.
20. The semiconductor substrate of claim 18 , wherein said at least one adhesive patch comprises at least one lateral edge exhibiting an angle of repose of approximately 20 degrees.
21. The semiconductor substrate of claim 18 , wherein said at least one adhesive patch comprises at least one trailing edge exhibiting an angle of repose of approximately 13 degrees.
22. The semiconductor substrate of claim 18 , wherein said at least one adhesive patch comprises at least one leading edge exhibiting an angle of repose of approximately 20 degrees.
23. A flip-chip including at least one laterally unconstrained conductive bump comprised of a viscous conductive material, the at least one conductive bump exhibiting a height-to-width ratio of at least approximately 3 to 1 and including a first surface adjacent and supported from beneath by said flip-chip and a second exposed surface opposite said first surface.
24. The flip-chip of claim 23 , wherein said viscous conductive material of said at least one conductive bump comprises at least one of the group consisting of a polyimide, a phenolic resin, a thermoplastic, and a thermosetting plastic.
25. The flip-chip of claim 23 , wherein said at least one conductive bump comprises at least one lateral edge exhibiting an angle of repose of approximately 20 degrees.
26. The flip-chip of claim 23 , wherein said at least one conductive bump comprises at least one trailing edge exhibiting an angle of repose of approximately 13 degrees.
27. The flip-chip of claim 23 , wherein said at least one conductive bump comprises at least one leading edge exhibiting an angle of repose of approximately 20 degrees.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 21, 1999
October 12, 2004
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