A command buffer for use in packetized DRAM includes a two stage shift register for shifting for sequentially storing two of four 10-bit command words in each packet. After the first two words of each packet have been stored, they are transferred to a first storage register and output from the first storage register. After the final two words of each packet have been shifted into the shift register, they are transferred to a second storage register and output from the second storage register. The first two command words are output from the first storage register before the last two command words are applied to the command buffer. As a result, the DRAM can start processing the first two command words of the command packet before the entire command packet has been received.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A command buffer for a memory device adapted to receive a command packet of N M-bit command words on an M-bit bus, N being an integer number greater than 1, the command buffer comprising: M shift registers each having an input terminal, an output terminal, and a clock terminal, the input terminal of each of the shift registers being coupled to a respective bit of the M-bit bus, each of the shift registers having N/Y stages, N/Y being a positive integer, a respective command word bit applied to the input terminal of each stage being shifted to an output terminal of each stage responsive to a clock signal adapted to be applied to the clock terminals of the shift registers; Y storage registers, where Y is an integer number greater than 1, each of the storage registers having (N/Y)*M storage cells, each of the storage cells having an output terminal, an input terminal coupled to the output terminal of a respective shift register stage, and a load terminal, each of the storage cells storing a signal at the output terminal of the respective shift register stage responsive to a load signal applied to the load terminal of the storage cell; and a control circuit having a clock terminal and at least one output terminal, the control circuit generating the load signals after each N/Y of the command words having been shifted into the shift registers, the load signals being sequentially applied to the load terminals of successive storage registers so that the storage registers each receive respective N/Y command words as N command words are shifted into the shift registers.
2. The command buffer of claim 1 wherein N is equal to 4 and Y is equal to 2 so that the shift registers each have two stages, and there are two storage registers each of which has 2*M storage cells.
3. The command buffer of claim 1 , further comprising a command decoder coupled to one of the storage registers that stores command words received from the shift registers before command words are stored in another shift register, the decoder decoding the command words stored in the storage register before command words have been stored in the other storage register.
4. The command buffer of claim 1 , further comprising a comparison circuit coupled to a first of the storage registers that stores command words received from the shift registers before command words are stored in a second shift register, the comparison circuit determining if at least a portion of the command word stored in the first storage register has a specific value and generating a select signal in response thereto, the comparison circuit comprising a latch storing the specific command word value and outputting a comparison word corresponding thereto; and a comparator having a first input coupled to the first storage register and a second input coupled to the latch, the comparator comparing the comparison word with at least a portion of the command word stored in the first storage register and generating the select signal responsive to a match between the comparison word and the portion of the command word.
5. The command buffer of claim 4 wherein the comparator compares the comparison word with the portion of the command word before N/Y command words are stored in the second shift register.
6. The command buffer of claim 4 wherein the comparator comprises an exclusive OR gate for each compared bit of the command word, each exclusive OR gate having a pair of input terminals receiving a bit of the comparison word and a corresponding bit of the command word, the exclusive OR gates collectively generating the select signal responsive to a match between all of the compared bits of the comparison word and the bits of the command word.
7. The command buffer of claim 1 , further comprising an enable circuit for generating a select signal that enables functions on an integrated circuit containing the command buffer, the enable circuit comprising: a first decoder circuit having an input bus coupled to one of the storage registers, the first decoder generating a load signal at an output terminal responsive to at least a portion of the command word having a predetermined value; an ID register having an input bus coupled to the respective output terminals of one of the storage registers, the ID register storing at least a portion of a command word received from the storage register responsive to the load signal and generating on an output bus a comparison word corresponding thereto; and a comparator having a first input bus coupled to a first of the storage registers that stores command words received from the shift registers before command words are stored in a second shift register, the comparator further having a second input bus coupled to the output bus of the ID register, the comparator comparing the comparison word with at least a portion of the command word received from the first storage register and generating the select signal responsive to a match between the comparison word and the portion of the command word.
8. The command buffer of claim 7 wherein the comparator comprises an exclusive OR gate for each compared bit of the command word received from the first storage register, each exclusive OR gate having a pair of input terminals receiving a bit of the comparison word and a corresponding bit of the command word, the exclusive OR gates collectively generating the select signal responsive to a match between all of the compared bits of the comparison word and the bits of the command word.
9. The command buffer of claim 1 wherein the command word bits applied to the input terminal of respective shift registers is shifted through two stages of the shift register for each cycle of the clock signal.
10. A command buffer comprising: a shift register having an input bus adapted to receive a four command word command packet, and a clock terminal adapted to receive a clock signal, the shift register having two stages with a command word applied to an input bus of each stage being shifted to an output bus of each stage responsive to the clock signal; first and second storage registers each of which has sufficient storage cells to store two command words, each of the storage cells having an output bus, an input bus coupled to the output bus of a respective shift register stage, and a load terminal, each of the storage registers storing command words received from the output buses of the respective shift register stages responsive to first and second load signals applied to the load terminal of the first and second storage registers, respectively; and a control circuit having a clock terminal and at least one output terminal, the control circuit generating the first load signal after the first two command words of each command packet have been shifted into the shift register and generating the second load signal after the second two command words of each command packet have been shifted into the shift register.
11. The command buffer of claim 10 , further comprising a command decoder coupled to the first storage register, the decoder decoding the command words of a command packet that are stored in the first storage register before command words of the command packet have been stored in the second storage register.
12. The command buffer of claim 10 , further comprising a comparison circuit coupled to a first storage register, the comparison circuit determining if at least a portion of the command word stored in the first storage register has a specific value and generating a select signal in response thereto, the comparison circuit comprising: a latch storing the specific command word value and outputting a comparison word corresponding thereto; and a comparator having a first input coupled to the first storage register and a second input coupled to the latch, the comparator comparing the comparison word with at least a portion of the command word stored in the first storage register and generating the select signal responsive to a match between the comparison word and the portion of the command word.
13. The command buffer of claim 12 wherein the comparator compares the comparison word with the portion of the command word before command words are stored in the second shift register.
14. The command buffer of claim 10 , further comprising an enable circuit for generating a select signal that enables functions on an integrated circuit containing the command buffer, the enable circuit comprising: a first decoder circuit having an input bus coupled to one of the storage registers, the first decoder generating a load signal at an output terminal responsive to at least a portion of the command word having a predetermined value; an ID register having an input bus coupled to the respective output terminals of one of the storage registers, the ID register storing at least a portion of a command word received from the storage register responsive to the load signal and generating on an output bus a comparison word corresponding thereto; and a comparator having a first input bus coupled to a first storage register and a second input bus coupled to the output bus of the ID register, the comparator comparing the comparison word with at least a portion of the command word received from the first storage register and generating the select signal responsive to a match between the comparison word and the portion of the command word.
15. The command buffer of claim 14 wherein the comparator compares the comparison word with the portion of the portion of the command word before command word in the command packet are stored in the second shift register.
16. The command buffer of claim 10 wherein the command words are shifted through two stages of the shift register for each cycle of the clock signal.
17. A memory device, comprising: at least one array of memory cells adapted to store data at a location determined by a row address and a column address responsive to a command word; a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to the command word; a column address circuit adapted to receive or apply data to one of the memory cells in the selected row corresponding to the column address responsive to the command word; a data path circuit adapted to couple data between an external terminal and the column address circuit responsive to the command word; and a command buffer adapted to receive N M-bit command words received on an M-bit bus, N being an integer number greater than 1, the command buffer comprising: M shift registers each having an input terminal, an output terminal, and a clock terminal, the input of each of the shift registers being coupled to a respective bit of the M-bit bus, each of the shift registers having N/Y stages, N/Y being a positive integer, a respective command word bit applied to the input terminal of each stage being shifted to an output terminal of each stage responsive to a clock signal adapted to be applied to the clock terminals of the shift registers; Y storage registers, where Y is an integer number greater than 1, each of the storage registers having (N/Y)*M storage cells, each of the storage cells having an output terminal, an input terminal coupled to the output terminal of a respective shift register stage, and a load terminal, each of the storage cells storing a signal at the output terminal of the respective shift register stage responsive to a load signal applied to the load terminal of the storage cell; and a control circuit having a clock terminal and at least one output terminal, the control circuit generating the load signals after each N/Y of the command words having been shifted into the shift registers, the load signals being sequentially applied to the load terminals of successive storage registers so that the storage registers each receive respective N/Y command words as N command words are shifted into the shift registers.
18. The memory device of claim 17 wherein N is equal to 4 and Y is equal to 2 so that the shift registers each have two stages, and there are two storage registers each of which has 2*M storage cells.
19. The memory device of claim 17 wherein N is equal to 8 and Y is equal to 2 so that the shift registers each have four stages, and there are two storage registers each of which has 4*M storage cells.
20. The memory device of claim 17 , further comprising a command decoder coupled to one of the storage registers that stores command words received from the shift registers before command words are stored in another shift register, the decoder decoding the command words stored in the storage register before command words have been stored in the other storage register.
21. The memory device of claim 17 , further comprising a comparison circuit coupled to a first of the storage registers that stores command words received from the shift registers before command words are stored in a second shift register, the comparison circuit determining if at least a portion of the command word stored in the first storage register has a specific value and generating a select signal in response thereto, the comparison circuit comprising: a latch storing the specific command word value and outputting a comparison word corresponding thereto; and a comparator having a first input coupled to the first storage register and a second input coupled to the latch, the comparator comparing the comparison word with at least a portion of the command word stored in the first storage register and generating the select signal responsive to a match between the comparison word and the portion of the command word.
22. The memory device of claim 21 wherein the comparator compares the comparison word with the portion of the command word before N/Y command words are stored in the second shift register.
23. The memory device of claim 21 wherein the comparator comprises an exclusive OR gate for each compared bit of the command word, each exclusive OR gate having a pair of input terminals receiving a bit of the comparison word and a corresponding bit of the command word, the exclusive OR gates collectively generating the select signal responsive to a match between all of the compared bits of the comparison word and to bits of the command word.
24. The memory device of claim 17 , further comprising an enable circuit for generating a select signal that enables functions in the memory device, the enable circuit comprising: a first decoder circuit having an input bus coupled to one of the storage registers, the first decoder generating a load signal at an output terminal responsive to at least a portion of the command word having a predetermined value; an ID register having an input bus coupled to the respective output terminals of one of the storage registers, the ID register storing at least a portion of a command word received from the storage register responsive to the load signal and generating on an output bus a comparison word corresponding thereto; and a comparator having a first input bus coupled to a first of the storage registers that stores command words received from the shift registers before command words are stored in a second shift register, the comparator further having a second input bus coupled to the output bus of the ID register, the comparator comparing the comparison word with at least a portion of the command word received from the first storage register and generating the select signal responsive to a match between the comparison word and the portion of the command word.
25. The memory device of claim 24 wherein the comparator comprises an exclusive OR gate for each compared bit of the command word received from the first storage register, each exclusive OR gate having a pair of input terminals receiving a bit of the comparison word and a corresponding bit of the command word, the exclusive OR gates collectively generating the select signal responsive to a match between all of the compared bits of the comparison word and the bits of the command word.
26. The memory device of claim 17 wherein the command word bits applied to the input terminal of respective shift registers is shifted through two stages of the shift register for each cycle of the clock signal.
27. The memory device of claim 17 wherein the memory device comprises a random access memory.
28. The memory device of claim 27 wherein the memory device comprises a dynamic random access memory.
29. The memory device of claim 28 wherein the memory device comprises a packetized dynamic random access memory.
30. A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and a memory device coupled to the processor through the processor bus, comprising: at least one array of memory cells adapted to store data at a location determined by a row address and a column address responsive to a command word; a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to the command word; a column address circuit adapted to receive or apply data to one of the memory cells in the selected row corresponding to the column address responsive to the command word; a data path circuit adapted to couple data between an external terminal and the column address circuit responsive to the command word; and a command buffer adapted to receive N M-bit command words received on an M-bit bus, N being an integer number greater than 1, the command buffer comprising: M shift registers each having an input terminal, an output terminal, and a clock terminal, the input of each of the shift registers being coupled to a respective bit of the M-bit bus, each of the shift registers having N/Y stages, N/Y being a positive integer, a respective command word bit applied to the input terminal of each stage being shifted to an output terminal of each stage responsive to a clock signal adapted to be applied to the clock terminals of the shift registers; Y storage registers, where Y is an integer number greater than 1, each of the storage registers having (N/Y)*M storage cells, each of the storage cells having an output terminal, an input terminal coupled to the output terminal of a respective shift register stage, and a load terminal, each of the storage cells storing a signal at the output terminal of the respective shift register stage responsive to a load signal applied to the load terminal of the storage cell; and a control circuit having a clock terminal and at least one output terminal, the control circuit generating the load signals after each N/Y of the command words having been shifted into the shift registers, the load signals being sequentially applied to the load terminals of successive storage registers so that the storage registers each receive respective N/Y command words as N command words are shifted into the shift registers.
31. The computer system of claim 30 wherein N is equal to 4 and Y is equal to 2 so that the shift registers each have two stages, and there are two storage registers each of which has 2*M storage cells.
32. The memory device of claim 30 wherein N is equal to 8 and Y is equal to 2 so that the shift registers each have four stages, and there are two storage registers each of which has 4*M storage cells.
33. The computer system of claim 30 further comprising a command decoder coupled to one of the storage registers that stores command words received from the shift registers before command words are stored in another shift register, the decoder decoding the command words stored in the storage register before command words have been stored in the other storage register.
34. The computer system of claim 30 , further comprising a comparison circuit coupled to a first of the storage registers that stores command words received from the shift registers before command words are stored in a second shift register, the comparison circuit determining if at least a portion of the command word stored in the first storage register has a specific value and generating a select signal in response thereto, the comparison circuit comprising: a latch storing the specific command word value and outputting a comparison word corresponding thereto; and a comparator having a first input coupled to the first storage register and a second input coupled to the latch, the comparator comparing the comparison word with at least a portion of the command word stored in the first storage register and generating the select signal responsive to a match between the comparison word and the portion of the command word.
35. The computer system of claim 34 wherein the comparator compares the comparison word with the portion of the command word before N/Y command words are stored in the second shift register.
36. The computer system of claim 34 wherein the comparator comprises an exclusive OR gate for each compared bit of the command word, each exclusive OR gate having a pair of input terminals receiving a bit of the comparison word and a corresponding bit of the command word, the exclusive OR gates collectively generating the select signal responsive to a match between all of the compared bits of the comparison word and the bits of the command word.
37. The computer system of claim 30 , further comprising an enable circuit for generating a select signal that enables functions in the memory device, the enable circuit comprising: a first decoder circuit having an input bus coupled to one of the storage registers, the first decoder generating a load signal at an output terminal responsive to at least a portion of the command word having a predetermined value; an ID register having an input bus coupled to the respective output terminals of one of the storage registers, the ID register storing at least a portion of a command word received from the storage register responsive to the load signal and generating on an output bus a comparison word corresponding thereto; and a comparator having a first input bus coupled to a first of the storage registers that stores command words received from the shift registers before command words are stored in a second shift register, the comparator further having a second input bus coupled to the output bus of the ID register, the comparator comparing the comparison word with at least a portion of the command word received from the first storage register and generating the select signal responsive to a match between the comparison word and the portion of the command word.
38. The computer system of claim 37 wherein the comparator comprises an exclusive OR gate for each compared bit of the command word received from the first storage register, each exclusive OR gate having a pair of input terminals receiving a bit of the comparison word and a corresponding bit of the command word, the exclusive OR gates collectively generating the select signal responsive to a match between all of the compared bits of the comparison word and the bits of the command word.
39. The computer system of claim 30 wherein the command word bits applied to the input terminal of respective shift registers is shifted through two stages of the shift register for each cycle of the clock signal.
40. The computer system of claim 30 wherein the memory device comprises a random access memory.
41. The computer system of claim 40 wherein the memory device comprises a dynamic random access memory.
42. The computer system of claim 41 wherein the memory device comprises a packetized dynamic random access memory.
43. A method of processing a command packet of N M-bit command words for use by a memory device, the method comprising: sequentially storing command words until N/Y command words have been stored, the number of command words N in the command packet being a positive integer greater than 1, and N/Y being a positive integer; each time N/Y command words have been stored, transferring the (N/Y)*M bits of the command words to one of Y respective storage locations, Y being a positive integer greater than 1; and outputting the command words from each of the Y storage locations.
44. The method of claim 43 wherein outputting the command words from each of the Y storage locations comprises outputting the command words from at least one of the storage locations before command words have been transferred to another of the storage locations.
45. The method of claim 44 , further comprising processing at least part of the command word transferred to the one storage location before command words have been transferred to the other storage location.
46. The method of claim 43 , further comprising: providing an identification word; and comparing at least a portion of a command word with the identification word, and, in the event of a match, performing an operation in the memory device that corresponds to another portion of a command word.
47. The method of claim 46 wherein comparing the portion of a command word with the identification word comprises comparing a portion of a command word that is transferred to one of the storage locations before the command word to which the operation corresponds is transferred to another of the storage locations.
48. The method of claim 46 wherein providing the identification word comprises: determining if at least a portion of the command word has a second predetermined value; and if at least a portion of the command word has a second predetermined value, storing at least a portion of a command word as to identification word.
49. The method of claim 43 wherein the memory device using the command words comprises a random access memory.
50. The method of claim 49 wherein the memory device using the command words comprises a dynamic random access memory.
51. The method of claim 50 wherein the memory device using the command words comprises a packetized dynamic random access memory.
52. In a computer system having a processor having a processor bus coupled to an input device, and output device, and a plurality of packetized memory devices, a method of processing a command packet of N M-bit command words in each of the memory devices for use by a memory device, the method comprising: sequentially storing command words in a plurality of the memory devices until N/Y command words have been stored, the number of command words N in the command packet being a positive integer greater than 1, and N/Y being a positive integer; each time N/Y command words have been stored, transferring the (N/Y)*M bits of the command words to one of Y respective storage locations, Y being a positive integer greater than 1; outputting the command words from each of the Y storage locations; providing respective identification words unique to each of the memory devices; comparing at least a portion of a command word output from one of the storage locations in a plurality of the memory devices with the respective identification words for the memory devices; and in the event of a match between the portion of a command word and an identification word in a memory device, performing an operation corresponding to a command word in the memory device having an identification word matching the portion of the command word.
53. The method of claim 52 wherein providing each of the identification words comprises: determining if at least a portion of the command word has a second predetermined value; and if at least a portion of the command word has a second predetermined value, storing at least a portion of the command word as the identification word.
54. The method of claim 52 wherein comparing the portion of a command word with the respective identification word comprises comparing a portion of a command words from at least one of the storage locations before command words have been transferred to another of the storage locations.
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November 6, 2002
October 12, 2004
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