Wafer-level package with a cavity and fabricating method thereof

1. A package, comprising: a chip having a micro device and a plurality of bonding pads electrically connected to the micro device; a substrate having a plurality of conductive through vias corresponding to and electrically connected to the bonding pads; and a seal member disposed between the chip and the substrate and surrounding the micro device and the bonding pads to define a cavity in which the micro device and the bonding pads are received wherein all of the bonding pads of the chip are in alignment with the respective vias of the substrate.

2. A package as claimed in claim 1 , further comprising, for each of the bonding pads, a conductive bump electrically connecting the bonding pad to the corresponding conductive via.

3. A package as claimed in claim 1 , wherein the seal member is an ACF (anisotropic conductive adhesive film) which covers the conductive bumps.

4. A package as claimed in claim 1 , wherein the seal member is epoxy resin.

5. A package as claimed in claim 1 , wherein the seal member is polyimide.

6. A package as claimed in claim 1 , wherein the substrate is selected from the group consisting of an organic substrate, a BT substrate and a glass substrate.

7. A package as claimed in claim 1 , wherein the substrate is made of single crystal silicon.

8. A package as claimed in claim 1 , wherein the micro device is selected from the group consisting of a integrated circuit, a micro mechanic device, a moving part and a sensor.

9. A package as claimed in claim 1 , wherein the substrate has a recess in a region corresponding to the cavity.

10. A method of fabricating a package at wafer-level, said method comprising the steps of: providing a wafer including a plurality of chips being separated from each other by first scribe lines, each of said chips having a micro device and a plurality of bonding pads electrically connected to the micro device; forming a plurality of conductive bumps on the bonding pads of the chips; forming a seal member surrounding the micro device, the bonding pads and the conductive bumps of each of the chips on the wafer; providing a substrate having second scribe lines corresponding to the first scribe lines of the wafer; forming a plurality of conductive vias in the substrate corresponding to the bonding pads of the chips on the wafer; aligning and bonding the wafer and the substrate together so that all of the conductive bumps on the wafer are in alignment with and electrically connected to the respective conductive vias of the substrate, and the seal members are disposed between the wafer and the substrate to form a plurality of hermetical cavities; and dicing the bonded wafer and substrate to form a plurality of individual packages.

11. The method as claimed in claim 10 , wherein the seal member is an ACF (anisotropic conductive adhesive film) which covers the conductive bumps.

12. The method as claimed in claim 10 , wherein the seal member is epoxy resin.

13. The method as claimed in claim 10 , wherein the seal member is polyimide.

14. The method as claimed in claim 10 , wherein the seal member is formed by a photolithographic process.

15. The method as claimed in claim 10 , wherein the step of forming the conductive vias further includes the following steps of: drilling the substrate to form a plurality of through vias; plating a conductive layer on the inner walls of the through vias; and filling the through vias with a conductive underfill material.

16. The method as claimed in claim 15 , wherein the step of forming the conductive vias further includes the following step of: reflowing the conductive underfill material for homogenizing the conductive underfill material.

17. The method as claimed in claim 15 , wherein the step of drilling the substrate is performed by one selected from the group consisting of mechanical drilling, laser drilling, photo-etching drilling and dry-etching drilling.

18. The method as claimed in claim 15 , wherein the conductive underfill material is selected from the group consisting of conductive epoxy, solder paste and silver paste.

19. The method as claimed in claim 10 , wherein the substrate is selected from the group consisting of organic substrate, a BT substrate and a glass substrate.

20. The method as claimed in claim 10 , wherein the substrate is made of single crystal silicon.

21. The method as claimed in claim 10 , further comprising the step of: forming a plurality of recesses on the substrate corresponding to the plurality of chips on the wafer.

22. The package as claimed in claim 1 , wherein the seal member is disposed on the edges of said chip.

23. The package as claimed in claim 2 , wherein the seal member is made of a conductive material which is in direct contact with the conductive bumps.

24. The method as claimed in claim 10 , wherein said dicing comprising cutting through said seal members.

25. The method as claimed in claim 10 , wherein said seal members are formed in regions corresponding to the first scribe lines, and said dicing includes cutting the wafer and the seal members along said first scribe lines.

26. The method as claimed in claim 10 , wherein the seal members are made of a conductive material which is in direct contact with the conductive bumps corresponding to said seal members.