The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice. Computing systems incorporating the packaging are also disclosed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device package, comprising: a plurality of semiconductor dice, each semiconductor die of the plurality having a back surface, an active surface and a plurality of signal connection devices on the active surface; a substrate having an attachment surface, an opposing surface and a plurality of openings formed therethrough, wherein each of the plurality of signal connection devices is positioned in one of the plurality of openings and the active surfaces of the plurality of semiconductor dice are adhered to the attachment surface of the substrate permitting exposure of the plurality of signal connection devices through the plurality of openings; and a molding layer disposed over the attachment surface of the substrate and the back surfaces of the plurality of semiconductor dice.
2. The semiconductor device package of claim 1 , further comprising: a first dielectric layer upon the opposing surface of the substrate; and a plurality of openings in the first dielectric layer exposing the plurality of signal connection devices therethrough.
3. The semiconductor device package of claim 2 , wherein the substrate includes a silicon wafer.
4. The semiconductor device package of claim 2 , wherein the plurality of signal connection devices is selected from the group consisting of gold stud bumps, copper stud bumps, and plated stud bumps.
5. The semiconductor device package of claim 2 , wherein each of the plurality of openings exhibits a depth which is at least as great as or greater than a height of each of the plurality of signal connection devices.
6. The semiconductor device package of claim 2 , further comprising a layer of die attach material disposed between and adhering the active surface of each of the plurality of semiconductor dice and the attachment surface of the substrate.
7. The semiconductor device package of claim 6 , wherein the layer of die attach material comprises an epoxy material.
8. The semiconductor device package of claim 6 , wherein the layer of die attach material comprises a polyimide material.
9. The semiconductor device package of claim 6 , wherein the layer of die attach material comprises benzocyclobutene.
10. The semiconductor device package of claim 6 , wherein the layer of die attach material exhibits a dielectric constant of up to about three.
11. The semiconductor device package of claim 2 , wherein the molding layer comprises a material which is capable of withstanding a temperature of up to about 300 C. without substantial degradation thereof.
12. The semiconductor device package of claim 2 , further comprising: a first circuit layer over the first dielectric layer electrically connected to the plurality of signal connection devices; at least one additional dielectric layer, having at least one additional plurality of openings formed therethrough; and at least one additional circuit layer over the at least one additional dielectric layer electrically coupled with the first circuit layer; an outermost dielectric layer having a plurality of holes formed therethrough, the outermost dielectric layer being disposed over the at least one additional circuit layer; and a plurality of conductive bumps disposed in the plurality of holes of the outermost dielectric layer and electrically coupled with the at least one additional circuit layer.
13. A memory device comprising: a carrier substrate; a plurality of electrical contacts coupled with electrical circuitry formed in the carrier substrate; and at least one semiconductor device package coupled with the electrical circuitry in the carrier substrate, the at least one semiconductor device package comprising: a plurality of semiconductor dice, each semiconductor die of the plurality having a back surface, an active surface and a plurality of signal connection devies on the active surface; a substrate having an attachment surface, an opposing surface and a plurality of openings formed therethrough, wherein each of the plurality of signal connection devices is positioned in one of the plurality of openings and the active surfaces of the plurality of semiconductor dice are adhered to the attachment surface of the substrate permitting exposure of the plurality of signal connection devices through the plurality of openings; and a molding layer disposed over the attachment surface of the substrate and the back surfaces of the plurality of semiconductor dice.
14. A computing system comprising: a carrier substrate; a processor operably coupled to the carrier substrate; at least one input device operably coupled with the carrier substrate; at least one output device operably coupled with the carrier substrate; and a memory device operably coupled to the carrier substrate, the memory device including at least one semiconductor device package, the at least one semiconductor device package comprising: a plurality of semiconductor dice, each semiconductor die having a back surface, an active surface and a plurality of signal connection devices on the active surface; a substrate having an attachment surface, an opposing surface and a plurality of openings formed therethrough, wherein each of the plurality of signal connection devices is positioned in one of the plurality of openings and the active surfaces of the plurality of semiconductor dice are adhered to the attachment surface of the substrate permitting exposure of the plurality of signal connection devices through the plurality of openings; and a molding layer disposed over the attachment surface of the substrate and the back surfaces of the plurality of semiconductor dice.
15. A semiconductor device package comprising: a plurality of semiconductor dice, each semiconductor die of the plurality having a back surface, an active surface and a plurality of signal connection devices on the active surface; a substrate having a plurality of cavities formed in a first surface of the substrate, wherein each semiconductor die of the plurality is disposed in one of the plurality of cavities with the back surface of each semiconductor die facing the base of its respective one of the plurality of cavities; a first dielectric layer disposed upon the first surface of the substrate and upon the active surface of each of the plurality of semiconductor dice; and a plurality of openings in the first dielectric layer exposing the plurality of signal connection devices.
16. The semiconductor device package of claim 15 , where the substrate comprises a silicon wafer.
17. The semiconductor device package of claim 15 , wherein the plurality of signal connection devices comprises bond pads.
18. The semiconductor device package of claim 15 , wherein each of the plurality of cavities exhibits a same depth which is at least equal to or greater than a height of each the plurality of semiconductor dice.
19. The semiconductor device package of claim 15 , further comprising a layer of die attach material disposed in the plurality of cavities and adhering the back surface of each of the plurality of semiconductor dice to the base of its respective one of the plurality of cavities.
20. The semiconductor device package of claim 19 , wherein the layer of die attach material comprises an epoxy material.
21. The semiconductor device package of claim 19 , where the layer of die attach material comprises a polyimide material.
22. The semiconductor device package of claim 19 , wherein the layer of die attach material comprises benzocyclobutene.
23. The semiconductor device package of claim 19 , wherein the layer of die attach material further comprises a material exhibiting a dielectric constant of up to about three.
24. The semiconductor device package of claim 15 , further comprising: a first circuit layer over the first dielectric layer electrically connected to the plurality of signal connection devices; at least one additional dielectric layer, having at least one additional plurality of openings formed therethrough; and at least one additional circuit layer over the at least one additional dielectric layer electrically coupled with the first circuit layer; an outermost dielectric layer having a plurality of holes formed therethrough, the outermost dielectric layer being disposed over the at least one additional circuit layer; and a plurality of conductive bumps disposed in the plurality of holes of the outermost dielectric layer and electrically coupled with the at least one additional circuit layer.
25. A memory device comprising: a printed circuit board; a plurality of electrical contacts coupled with electrical circuitry formed in the printed circuit board; and at least one semiconductor device package coupled with the electrical circuitry in the printed circuit board, the at least one semiconductor device package comprising: a plurality of semiconductor dice, each semiconductor die of the plurality having a back surface, an active surface and a plurality of signal connection devcies on the active surface; a substrate having a plurality of cavities formed in a first surface of the substrate, wherein each semiconductor die of the plurality is disposed in one of the plurality of cavities with the back surface of each semiconductor die facing the base of its respective one of the plurality of cavities; a first dielectric layer disposed upon the first surface of the substrate and upon the active surface of each of the plurality of semiconductor dice; and a plurality of openings in the first dielectric layer exposing the plurality of signal connection devices.
26. A computing system comprising: a printed circuit board; a processor operably coupled to the printed circuit board; at least one input device operably coupled with the printed circuit board; at least one output device operably coupled with the printed circuit board; and a memory device operably coupled to the printed circuit board, the memory device including at least one semiconductor device package, the at least one semiconductor device package comprising: a plurality of semiconductor dice, each semiconductor die of the plurality having a back surface, an active surface and a plurality of signal connection devices on the active surface; a substrate having a plurality of cavities formed in a first surface thereof, wherein each semiconductor die of the plurality is disposed in one of the plurality of cavities with the back surface of each semiconductor die facing the base of its respective one of the plurality of cavities; a first dielectric layer disposed upon the first surface of the substrate and upon the active surface of each of the plurality of semiconductor dice; and a plurality of openings in the first dielectric layer exposing the plurality of signal connection devices.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 5, 2003
November 30, 2004
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