A memory cell array is divided into a plurality of areas in a row direction. A group consisting of data writing latch circuits is connected to memory cells in a group consisting of the memory cells arranged in each of the areas, respectively, via a word line. Data lines are individually connected to the latch circuits. Sub word lines are connected commonly to the group consisting of the memory cells at each of the areas. A switching element for a word line is inserted between each of the sub word lines and a main word line. The switching element for the word line is turned on at the area, at which data latching is completed, so as to transmit a potential of a main word line to the sub word line, so that a writing operation is started without waiting for completion of data latching at the other area.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor storage apparatus comprising: a plurality of areas, each of which is divided in a memory cell array in a row direction; a group consisting of memory cells arranged in each of the areas; a group consisting of data writing latch circuits arranged in each of the areas in connection to each of the memory cells in the group consisting of the memory cells via a word line; data lines individually connected to the latch circuits, respectively; sub word lines connected commonly to the group consisting of the memory cells at each of the areas; and a switching element for a word line inserted between each of the sub word lines and a main word line.
2. A semiconductor storage apparatus as claimed in claim 1 , further comprising memory cells for storing therein a writing speed priority, interposed between bit lines, respectively.
3. A semiconductor storage apparatus comprising: a plurality of areas, each of which is divided in a memory cell array in a row direction; a group consisting of memory cells arranged in each of the areas; a group consisting of data writing latch circuits arranged in each of the areas in connection to each of the memory cells in the group consisting of the memory cells via a word line; data lines individually connected to the latch circuits, respectively; sub word lines connected commonly to-the group consisting of the memory cells at each of the areas; a switching element for a word line inserted between each of the sub word lines and a main word line; a switching element for a latch circuit interposed between each of the memory cells and each of the latch circuits; and an address signal line connected commonly to a group consisting of the switching elements for the latch circuits at each of the areas.
4. A semiconductor storage apparatus as claimed in claim 3 , further comprising memory cells for storing therein a writing speed priority, interposed between bit lines, respectively.
5. A writing method in a semiconductor storage apparatus, in which latch setting of writing data is sequentially performed per area in the state in which a memory cell array is divided into a plurality of areas in a row direction, the writing method comprising the steps of: performing latch setting of writing data at a certain area; and transferring and writing, to and in a memory cell of the area, data after the latch setting at the area, at which the latch setting is completed, performing the latch setting of the writing data at one of the residual areas, and further, sequentially shifting the simultaneous processing of the data writing and the data latch setting to a next area till completion at all of the areas.
6. A writing method in a semiconductor storage apparatus as claimed in claim 5 , wherein a data writing operation to be performed at the area, at which the latch setting is completed, during latch setting at the other area is a weak writing operation at a low level that the memory cell cannot reach a predetermined threshold level by making a potential level of the word line lower than that during a normal writing operation.
7. A writing method in a semiconductor storage apparatus as claimed in claim 5 , wherein a data writing operation to be performed at the area, at which the latch setting is completed, during latch setting at the other area is a weak writing operation at a low level that the memory cell cannot reach a predetermined threshold level by making a writing pulse width less than that during a normal writing operation.
8. A writing method in a semiconductor storage apparatus as claimed in claim 5 , wherein the electric connection between each of the latch circuits and each of the memory cells is cut at the area, at which the data writing operation is completed, and then, the latch setting of next writing data is performed during the data writing operation at the other area.
9. A writing method in a semiconductor storage apparatus as claimed in claim 5 , wherein information on a writing speed priority per area is stored during the data writing operation with respect to the memory cell, and the data writing operation is performed while giving priority to the area of a low priority based on the stored information on the writing speed priority during the second and thereafter writing operations after the completion of the data writing operation at all of the areas.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 13, 2003
November 30, 2004
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