A system includes a digital phase lock loop (PLL) constructed from an all digital circuit implementation and standard cell construction. The digital PLL includes a digital frequency synthesizer and a digital phase detector. The digital frequency synthesizer includes a digital DLL including a plurality of delay chains, each of the delay chains including at least one digitally programmable delay element for configuring the plurality of delay chains to achieve a phase lock with an input reference signal. The digital frequency synthesizer also a non-glitching MUX electrically coupled to the digital DLL for selecting a tap output from one of the at least one digitally programmable delay element to select at least one pulse glitch-free from the selected output tap, and a phase accumulator electrically coupled to the non-glitching MUX for precisely dividing a timing period of the input reference signal and for selecting a tap output from one of the at least one digitally programmable delay element to select at least one pulse at a precise point in the timing period from the output tap. The digital phase detector, is electrically coupled to the digital frequency synthesizer to compare an edge of the input reference signal to an edge of a synthesized signal to provide a digital code information representing a phase error between the edge of the input reference signal and the edge of the synthesized signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A digital phase lock loop comprising: an electrical input for receiving an input reference signal; an electrical output for providing an output signal that is a digitally generated synthesized version of the input reference signal; a control circuit; a digital phase detector, electrically coupled to the electrical input, the electrical output, and the control circuit, to compare an edge of the input reference signal to an edge of the output signal to provide a digital code information representing a phase error between the edge of the input reference signal and the edge of the output signal, and wherein the digital phase detector comprises a first delay chain arranged to be driven by the input reference signal and a second delay chain arranged to be driven by the output signal and in opposing timing orientation to the first delay chain, the arrangement of delay elements in the first and second delay chains, respectively, for providing a comparison of the edge of the input reference signal relative to the edge of the output signal; and a digital frequency synthesizer, being electrically coupled to the control circuit and the digital phase detector, the digital frequency synthesizer comprising: a reference clock input for receiving a reference clock signal; a digital DLL, electrically coupled to the control circuit and the reference clock input, the digital DLL including a plurality of delay chains, each of the delay chains including at least one digitally programmable delay element for the control circuit dynamically configuring the plurality of delay chains for the output signal to achieve a phase lock with the input reference signal; a phase accumulator, electrically coupled to the digital DLL, the digital phase detector, and the control circuit, for precisely dividing a timing period of the input reference signal; and a non-glitching MUX electrically coupled to the digital DLL, the phase accumulator, and the electrical output, for selecting a tap output from one of the at least one digitally programmable delay element to select glitch-free a first signal comprising at least one pulse from the selected output tap.
2. The digital phase lock loop of claim 1 , wherein the selected first signal comprising at least one pulse corresponds to the output signal.
3. The digital phase lock loop of claim 1 , further comprising: a digital controller electrically coupled to the digital phase detector and the digital frequency synthesizer; and a memory electrically coupled to the digital controller, and including instructions for the digital controller to control the digital frequency synthesizer to generate the first signal; and use the digital code to control the digital frequency synthesizer to adjust the phase of the output signal to match a phase of the input reference signal.
4. The digital phase lock loop of claim 3 , wherein the memory further includes instructions for the digital controller to perform a digital loop filter function on the digital code information.
5. The digital phase lock loop of claim 4 , wherein the digital loop filter function comprises a low pass filter function.
6. The digital phase lock loop of claim 1 , wherein the digital DLL, the non-glitching MUX, the phase accumulator, and digital phase detector, are all constructed using an all digital circuit implementation.
7. The digital phase lock loop of claim 6 , wherein the all digital circuit implementation comprises standard cell construction for an integrated circuit.
8. The digital phase lock loop of claim 1 , wherein the digital DLL, the non-glitching MUX, the phase accumulator, and the digital phase detector, are incorporated into an integrated circuit.
9. The digital phase lock loop of claim 1 , wherein the input reference signal is a reference horizontal sync signal and the output signal is a synthesized horizontal sync signal for driving a display monitor.
10. A system comprising: a system controller; a first input for receiving an input reference signal with a first edge; and a digital phase lock loop, electrically coupled to the system controller and to the first input, comprising: an electrical input, electrically coupled to the first input, for receiving the input reference signal; an electrical output for providing an output signal that is a digitally generated synthesized version of the input reference signal; a control circuit; a digital phase detector, electrically coupled to the electrical input, the electrical output, and the control circuit, to compare an edge of the input reference signal to an edge of the output signal to provide a digital code information representing a phase error between the edge of the input reference signal and the edge of the output signal, and wherein the digital phase detector comprises a first delay chain arranged to be driven by the input reference signal and a second delay chain arranged to be driven by the output signal and in opposing timing orientation to the first delay chain, the arrangement of delay elements in the first and second delay chains, respectively, for providing a comparison of the edge of the input reference signal relative to the edge of the output signal; and a digital frequency synthesizer, being electrically coupled to the control circuit and the digital phase detector, the digital frequency synthesizer comprising: a reference clock input for receiving a reference clock signal; a digital DLL, electrically coupled to the control circuit and the reference clock input, the digital DLL including a plurality of delay chains, each of the delay chains including at least one digitally programmable delay element for the control circuit dynamically configuring the plurality of delay chains for the output signal to achieve a phase lock with an the input reference signal; a phase accumulator, electrically coupled to the digital DLL, the digital phase detector, and the control circuit, for precisely dividing a timing period of the input reference signal; and a non-glitching MUX electrically coupled to the digital DLL, the phase accumulator, and the electrical output, for selecting a tap output from one of the at least one digitally programmable delay element to select glitch-free a first signal comprising at least one pulse from the selected output tap.
11. The system of claim 10 , wherein the selected first signal comprising at least one pulse corresponds to the output signal.
12. The system of claim 10 , further comprising: a digital controller electrically coupled to the digital phase detector and the digital frequency synthesizer; and a memory electrically coupled to the digital controller, and including instruction for the digital controller to control the digital frequency synthesizer to generate the first signal; and use the digital code to control the digital frequency synthesizer to adjust the phase of the output signal to match a phase of the input reference signal.
13. The system of claim 12 , wherein the memory further includes instructions for the digital controller to perform a digital loop filter function on the digital code information.
14. The system of claim 13 , wherein the digital loop filter function comprises a low pass filter function.
15. The system of claim 10 , wherein the digital DLL, the non-glitching MUX, the phase accumulator, and digital phase detector, are all constructed using an all digital circuit implementation.
16. The system of claim 15 , wherein the all digital circuit implementation comprises standard cell construction for an integrated circuit.
17. The system of claim 10 , wherein the digital DLL, the non-glitching MUX, the phase accumulator, and the digital phase detector, are incorporated into an integrated circuit.
18. The digital phase lock loop of claim 10 , wherein the input reference signal is a reference horizontal sync signal and the output signal is a synthesized horizontal sync signal for driving a display monitor.
19. A flat panel monitor comprising: a controller for controlling functions of the flat panel monitor; a display for displaying information; a video interface including a first input for receiving an input reference signal with a first edge; and a digital phase lock loop, electrically coupled to the video interface, the controller, and the display, the digital phase lock loop comprising: an electrical input, electrically coupled to the first input, for receiving the input reference signal; an electrical output for providing an output signal that is a digitally generated synthesized version of the input reference signal; a control circuit: a digital phase detector, electrically coupled to the electrical input, the electrical output, and the control circuit, to compare an edge of the input reference signal to an edge of the output signal to provide a digital code information representing a phase error between the edge of the input reference signal and the edge of the output signal, and wherein the digital phase detector comprises a first delay chain arranged to be driven by the input reference signal and a second delay chain arranged to be driven by the output signal and in opposing timing orientation to the first delay chain, the arrangement of delay elements in the first and second delay chains, respectively, for providing a comparison of the edge of the input reference signal relative to the edge of the output signal; and a digital frequency synthesizer, being electrically coupled to the control circuit and the digital phase detector, the digital frequency synthesizer comprising: a reference clock input for receiving a reference clock signal; a digital DLL, electrically coupled to the control circuit and the reference clock input, the digital DLL including a plurality of delay chains, each of the delay chains including at least one digitally programmable delay element for the control circuit dynamically configuring the plurality of delay chains for the output signal to achieve a phase lock with the input reference signal; a phase accumulator, electrically coupled to the digital DLL, the digital phase detector, and the control circuit, for precisely dividing a timing period of the input reference signal; and a non-glitching MUX electrically coupled to the digital DLL, the phase accumulator, and the electrical output, for selecting a tap output from one of the at least one digitally programmable delay element to select glitch-free a first signal comprising at least one pulse from the selected output tap.
20. The flat panel monitor of claim 19 , wherein the selected first signal comprising at least one pulse corresponds to the output signal.
21. The flat panel monitor of claim 19 , further comprising: a digital controller electrically coupled to the digital phase detector and the digital frequency synthesizer; and a memory electrically coupled to the digital controller, and including instructions for the digital controller to control the digital frequency synthesizer to generate the first signal; and use the digital code to control the digital frequency synthesizer to adjust the phase of the output signal to match a phase of the input reference signal.
22. The flat panel monitor of claim 21 , wherein the memory further includes instructions for the digital controller to perform a digital loop filter function on the digital code information.
23. The flat panel monitor of claim 22 , wherein the digital loop filter function comprises a low pass filter function.
24. The flat panel monitor of claim 19 , wherein the digital DLL, the non-glitching MUX, the phase accumulator, and digital phase detector, are all constructed using an all digital circuit implementation.
25. The flat panel monitor of claim 24 , wherein the all digital circuit implementation comprises standard cell construction for an integrated circuit.
26. The flat panel monitor of claim 19 , wherein the digital DLL, the non-glitching MUX, the phase accumulator, and the digital phase detector, are incorporated into an integrated circuit.
27. The flat panel monitor of claim 19 , wherein the input reference signal is a reference horizontal sync signal and the output signal is a synthesized horizontal sync signal for driving the display.
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March 24, 2000
November 30, 2004
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