A symmetric multiprocessor data processing system having a highly scalable shared cache memory hierarchy is disclosed. The symmetric multiprocessor data processing system includes multiple processing units. Each of the processing units includes a level one cache memory. All the level one cache memories are associated with a level two cache memory. The level two cache memory is non-inclusive of all the level one cache memories. An invalidation bus is connected to all of the level one cache memories. In response to a write access to a specific cache line within one of the level one cache memories, the invalidation bus invalidates other cache lines that shared identical information with the specific cache line within the rest of the level one cache memories.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A data processing system, comprising: a plurality of processing units; a plurality of level one cache memories, wherein ones of said plurality of level one cache memories are associated with respective ones of said plurality of processing units, wherein said plurality of level one cache memories are non-blocking cache memories that do not allow retry operations; a level two cache memory associated with said plurality of level one cache memories, wherein said level two cache memory is non-inclusive of said plurality of level one cache memories; and an invalidation bus, connected to said plurality of level one cache memories, for invalidating, in response to a STORE operation on a specific cache line within one of said plurality of level one cache memories, cache lines that share identical information with said specific cache line.
2. The data processing system of claim 1 , wherein said invalidation bus includes an Invalidation 13 Val line and a plurality of Invalidation_Addr lines.
3. The data processing system of claim 1 , wherein said invalidation bus is connected to said plurality of level one cache memories in a multi-drop manner.
4. The data processing system of claim 1 , wherein said invalidation bus is connected to said plurality of level one cache memories in a daisy-chain manner.
5. A method for invalidating multiple cache lines within a multi-level memory hierarchy within a data processing system having a plurality of processing units, said method comprising: associating a level one cache memory with a respective one of said plurality of processing units, wherein said plurality of level one cache memories are non-blocking cache memories that do not allow retry operations; associating a level two cache memory with said plurality of level one cache memories, wherein said level two cache memory is non-inclusive of said plurality of level one cache memories; and in response to a STORE operation on a specific cache line within one of said plurality of level one cache memories, invalidating cache lines that shared identical information with said specific cache line within the rest of said plurality of level one cache memories by utilizing an invalidation bus connected to said plurality of level one cache memories.
6. The method according to claim 5 , wherein said invalidation bus includes an Invalidation_Val line and a plurality of invalidation_Addr lines.
7. The method according to claim 5 , wherein said method further includes connecting said invalidation bus to said plurality of level one cache memories in a multi-drop manner.
8. The method according to claim 5 , wherein said method further includes connecting said invalidation bus to said plurality of level one cache memories in a daisy-chain manner.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 8, 2002
November 30, 2004
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