After forming, on a substrate, a first insulating film with a relatively low dielectric constant and low mechanical strength, the first insulating film is patterned. After forming, on the substrate, a second insulating film with a relatively high dielectric constant and high mechanical strength, the second insulating film is planarized by polishing, so as to form a thinned portion of the second insulating film on the patterned first insulating film. An interconnect groove is formed in the thinned portion of the second insulating film and the patterned first insulating film, and then, a buried interconnect is formed in the interconnect groove.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for fabricating a semiconductor device comprising the steps of: forming on a substrate, a first insulating film with a relatively low dielectric constant and low mechanical strength; partially retaining said first insulating film in a first region through selective etching using a first mask pattern formed on said first insulating film; forming a second insulating film with a relatively high dielectric constant and high mechanical strength, such that said second insulating film covers said retained first insulating film; forming a thinned portion of said second insulating film on said retained first insulating film by planarizing said second insulating film by polishing; forming a first interconnect groove in said thinned portion of said second insulating film and said retained first insulating film through selective etching said thinned portion of said second insulating film and said retained first insulating film using a second mask pattern formed on said thinned portion of said second insulating film; and forming a buried interconnect in said first interconnect groove, wherein said thinned portion of said second insulating film and said retained first insulating film are provided on the sides of said buried interconnect, said first insulating film includes an organic material as a principal constituent and said second insulating film includes an inorganic material as a principal constituent, the step of forming said first interconnect groove includes a sub-step of forming a second interconnect groove in a second region, which is different from the first region, of said second insulating film through selective etching using said second mask pattern in forming an upper portion of said first interconnect groove in said thinned portion of said second insulating film through the selective etching using said second mask pattern, and the step of forming said first interconnect groove includes a sub-step of removing said second mask pattern in forming a lower portion of said first interconnect groove in said first insulating film.
2. A method for fabricating a semiconductor device comprising the steps of: forming, on a substrate, a first insulating film with a relatively low dielectric constant and low mechanical strength; partially retaining said first insulating film in a first region through selective etching using a first mask pattern formed on said first insulating film; forming a second insulating film with a relatively high dielectric constant and high mechanical strength, such that said second insulating film covers said retained first insulating film; forming a thinned portion of said second insulating film on said retained first insulating film by planarizing said second insulating film by polishing; forming a first interconnect groove in said thinned portion of said second insulating film and said retained first insulating film through selective etching said thinned portion of said second insulating film and said retained first insulating film using a second mask pattern formed on said thinned portion of said second insulating film; and forming a buried interconnect in said first interconnect groove, wherein said thinned portion of said second insulating film and said retained first insulating film are provided on the sides of said buried interconnect, and wherein said thinned portion of said second insulating film has a thickness of 10 nm through 50 nm.
3. A method for fabricating a semiconductor device comprising the steps of: forming on a substrate, a first insulating film with a relatively low dielectric constant and low mechanical strength; partially retaining said first insulating film in a first region through selective etching using a first mask pattern formed on said first insulating film; forming a second insulating film with a relatively high dielectric constant and high mechanical strength, such that said second insulating film covers said retained first insulating film; forming a thinned portion of said second insulating film on said retained first insulating film by planarizing said second insulating film by polishing; forming a first interconnect groove in said thinned portion of said second insulating film and said retained first insulating film through selective etching said thinned portion of said second insulating film and said retained first insulating film using a second mask pattern formed on said thinned portion of said second insulating film; and forming a buried interconnect in said first interconnect groove, wherein said thinned portion of said second insulating film and said retained first insulating film are provided on the sides of said buried interconnect, and a thickness of said thinned portion of said second insulating film in said first region is smaller than a thickness of said second insulating film in a second region, which is different from said first region.
4. The method for fabricating a semiconductor device of claim 3 , further comprising a step of forming, on said buried interconnect, a third insulating film for preventing diffusion of a metal included in said buried interconnect.
5. The method for fabricating a semiconductor device of claim 3 , wherein both of said first insulating film and said second insulating film include inorganic materials as principal constituents, and the step of forming said first interconnect groove includes a sub-step of forming a second interconnect groove in a second region, which is different from the first region, of said second insulating film through selective etching using said second mask pattern.
6. The method for fabricating a semiconductor device of claim 3 , wherein the step of forming said first interconnect groove includes a sub-step of forming a second interconnect groove in a second region, which is different from said first region, of said second insulating film through selective etching of said second insulating film using said second mask pattern.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 31, 2001
December 28, 2004
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