Embodiments of the present invention provide a memory system. In one embodiment, the memory system comprises an array of memory cells, a write circuit configured to write memory cells in the array of memory cells and a control circuit. The control circuit is configured to receive data, provide encoded received data to match a fault pattern in the array of memory cells, and control the write circuit to write the encoded received data into the array of memory cells at a fault address of the fault pattern.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory system, comprising: an array of memory cells; a write circuit configured to write memory cells in the array of memory cells; and a control circuit configured to receive data, provide encoded received data to match a fault pattern in the array of memory cells, and control the write circuit to write the encoded received data into the array of memory cells at a fault address of the fault pattern.
2. The memory system of claim 1 , where the control circuit is configured to provide encoded received data comprising the received data.
3. The memory system of claim 1 , where the control circuit is configured to provide encoded received data comprising rearranged received data.
4. The memory system of claim 1 , where the control circuit is configured to provide encoded received data comprising inverted received data.
5. The memory system of claim 1 , where the control circuit is configured to provide encoded received data comprising the received data encoded with a mathematical operation.
6. The memory system of claim 1 , where the control circuit is configured to provide encoded received data comprising convoluted received data.
7. The memory system of claim 1 , where the control circuit is configured to provide encoded received data comprising the received data encoded with a matrix multiply.
8. The memory system of claim 1 , where the control circuit is configured to provide encoding information to the write circuit that writes the encoded received data comprising the encoding information into the array of memory cells at the fault address of the fault pattern.
9. The memory system of claim 1 , where the fault pattern is stored in a fault map of the array of memory cells.
10. The memory system of claim 1 , where the fault pattern is marked as used as the encoded received data is written into the array of memory cells at the fault address of the fault pattern.
11. The memory system of claim 1 , where the control circuit is configured to receive a write address for writing the received data to the write address, control the write circuit to write the encoded received data to the fault address and write an address map to indicate the write address corresponds to the fault address.
12. The memory system of claim 1 , comprising a read circuit configured to read memory cells in the array of memory cells, where the control circuit is configured to receive a read address for reading the array of memory cells, look up the read address and a corresponding fault address and control the read circuit to read at the corresponding fault address.
13. The memory system of claim 1 , comprising a read circuit configured to read memory cells in the array of memory cells, where the control circuit is configured to receive encoded received data comprising encoding information from the array of memory cells and decode the encoded received data using the encoding information to obtain the received data.
14. A memory system, comprising: a magnetic memory; and a control circuit configured to compare a data pattern to a fault pattern in a section of the magnetic memory and write the data pattern to the section of the magnetic memory if the data pattern matches the fault pattern.
15. The memory system of claim 14 , where the control circuit is configured to retrieve the fault pattern from a fault map that is stored in non-volatile memory.
16. The memory system of claim 14 , where the control circuit is configured to retrieve a fault address of the section of the magnetic memory from a fault map that is stored in non-volatile memory to write the data pattern into the magnetic memory at the fault address.
17. The memory system of claim 14 , where the control circuit is configured to store a fault address of the section of the magnetic memory in an address map that is stored in non-volatile memory.
18. The memory system of claim 14 , where the control circuit is configured to retrieve a fault address of the section of the magnetic memory from an address map that is stored in non-volatile memory to read the data pattern from the magnetic memory.
19. The memory system of claim 14 , where the control circuit is configured to receive data and provide encoded received data as the data pattern.
20. The memory system of claim 14 , where the control circuit is configured to provide encoding information that indicates encoding of the data pattern as part of the data pattern to compare to the fault pattern.
21. The memory system of claim 14 , where the control circuit is configured to receive data and a write address, encode the received data to provide the data pattern, and in the event the data pattern matches the fault pattern, write the data pattern to a fault address of the section of the magnetic memory and provide an address map entry indicating the write address corresponds to the fault address.
22. The memory system of claim 14 , where the control circuit is configured to read the magnetic memory, receive the data pattern with encoding information and decode the data pattern using the encoding information.
23. A magnetic memory, comprising: means for encoding received data; means for matching the encoded data to fault patterns in sections of the magnetic memory; and means for storing the encoded data at matching fault pattern locations in the magnetic memory.
24. The magnetic memory of claim 23 , where the means for encoding received data is configured to change a bit pattern of the received data.
25. The magnetic memory of claim 23 , where the means for encoding received data is configured to leave bit patterns of the received data as received.
26. The magnetic memory of claim 23 , where the means for encoding received data is configured to provide a plurality of encoding schemes for encoding the received data.
27. The magnetic memory of claim 23 , where the means for matching the encoded data is configured to compare the received data encoded in a plurality of encoding schemes.
28. The magnetic memory of claim 23 , where the means for storing the encoded data is configured to store the encoded data comprising encoding information at the matching fault pattern locations in the magnetic memory.
29. A method of storing data in a memory, comprising: receiving data; matching the received data to hard faults in a section of the memory; and writing the matched received data into the section of the memory.
30. The method of claim 29 , comprising: providing encoding information that indicates how the received data was matched to the hard faults; and writing the encoding information into another memory.
31. The method of claim 29 , where matching the received data comprises changing the received data bit patterns to match the hard faults.
32. The method of claim 29 , comprising: receiving a write address; writing the matched received data to a fault address that indicates the location of the section in the memory; and writing an address map to indicate the write address corresponds to the fault address.
33. The method of claim 29 , comprising: receiving a read address; looking up the read address and a corresponding address in an address map; and reading the memory at the corresponding address.
34. The method of claim 29 , comprising: reading the matched received data from the memory; reading encoding information; and decoding the matched received data using the encoding information to obtain the received data.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 4, 2003
January 4, 2005
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.