A process for manufacturing an integrated device comprises the steps of: forming, in a first wafer of semiconductor material, integrated structures including semiconductor regions and isolation regions; forming, on a second wafer of semiconductor material, interconnection structures of a metal material including plug elements having at least one bonding region of a metal material capable of reacting with the semiconductor regions of the first wafer; and bonding the first and second wafers together by causing the bonding regions of the plug elements to react directly with the semiconductor regions so as to form a metal silicide. Thereby, the metallurgical operations for forming the interconnection structures are completely independent of the operations required for processing silicon, so that there is no interference whatsoever between the two sets of operations. In addition, the areas where the two wafers are made may be separate, and the interconnection structures may be made with materials incompatible with silicon processing, without any risk of contamination.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A process for manufacturing an integrated device, comprising: forming integrated structures including semiconductor regions and isolation regions at a first wafer of semiconductor material; forming interconnection structures of conductor material on a second wafer of semiconductor material, including forming plug elements, each including a base region and a bonding region, the bonding region of a metal material different from the base region and capable of reacting with said semiconductor regions of said first wafer; and bonding said first wafer and said second wafer together, including causing said bonding regions to react with said semiconductor regions.
2. The process according to claim 1 , wherein said semiconductor material is silicon, and said step of causing said bonding region to react comprises forming a metal silicide.
3. The process according to claim 1 , wherein said metal material is chosen from among titanium, nickel, platinum, palladium, tungsten, and cobalt.
4. The process according to claim 1 , wherein said plug elements have a height, and said step of forming integrated structures comprises forming an insulating material layer on top of the first wafer, said insulating material layer having a thickness smaller than said height of said plug elements, and forming openings in said insulating material layer to uncover selective portions of said wafer, and wherein said step of bonding said first and second wafers comprises causing said bonding region to react with at least said selective portions of said wafer.
5. The process according to claim 1 , wherein said step of forming integrated structures comprises forming an insulating material layer on top of the first wafer, and forming conductive regions of semiconductor material on top of said insulating material layer, and said step of bonding said first and second wafers comprises causing said bonding region to react with said conductive regions.
6. The process according to claim 1 , wherein said step of forming interconnection structures comprises forming electrical connection regions of conductive material, and said step of forming plug elements comprises forming base regions of conductive material on top of and in direct electrical contact with said electrical connections regions, and forming said bonding regions on top of said base regions.
7. The process according to claim 1 , wherein said step of forming integrated structures comprises forming integrated electronic components.
8. The process according to claim 1 , wherein said step of forming integrated structures comprises forming micro-electromechanical systems.
9. The process according to claim 1 , further comprising, before said step of bonding said first and second wafers, the step of forming self-alignment structures on said first and second wafers, and aligning said first and second wafers, using said self-alignment structures.
10. The process according to claim 9 , wherein said step of forming self-alignment structures comprises forming at least one engagement seat in one of said first and second wafers, and forming at least one engagement element on another of said first and second wafers in a position facing said engagement seat.
11. The process according to claim 10 , wherein said step of forming integrated structures comprises forming an insulating material layer on top of the first wafer, said step of forming at least one engagement seat comprises forming a guide opening in said insulating material layer, said guide opening having a basically trapezium shape, with a major base and a minor base, and said engagement element having transverse dimensions smaller than said major base and greater than said minor base, and said step of aligning said first and second wafers comprises inserting said engagement element into said guide opening near said major base and displacing said second wafer with respect to said first wafer so to bring said engagement element towards said guide opening until said engagement element slots into said engagement seat.
12. The process according to claim 11 , wherein said step of forming at least one engagement seat comprises forming a notch in said substrate beneath said guide opening, said step of forming an engagement element comprises forming at least one pin element of greater height than the thickness of said insulating material layer, and said step of displacing said second wafer comprises causing said pin element to snap into said notch before fittedly engaging said engagement element into said slotting seat.
13. The process of claim 1 wherein said metal material is palladium.
14. The process of claim 1 , further comprising forming a through opening in the second wafer on a side of the wafer opposite the interconnecting structures, such that a portion of an interconnection structure is exposed.
15. The process of claim 14 , further comprising attaching a connection wire to the interconnection structure via the through opening.
16. A process for manufacturing an integrated device, comprising: forming integrated structures in a first wafer of semiconductor material, the first wafer including an exposed semiconductor region; forming, on a second wafer of semiconductor material, a plug element, including a base region and a bonding region, the bonding region being of a metal material different from base region; and bonding the first and second wafers together by causing the bonding region of the plug element to react with the exposed semiconductor region.
17. A process for manufacturing an integrated device, comprising: forming integrated structures including semiconductor regions and isolation regions in a first wafer of semiconductor material; forming interconnection structures of conductor material on a second wafer of semiconductor material, including forming plug elements, each having a bonding region of a metal material capable of reacting with said semiconductor regions of said first wafer; forming a plurality of conductive regions on the second wafer; forming connection regions connecting the conductive regions together; forming one of the plug elements connected to one of the plurality of conductive regions; and bonding said first wafer and said second wafer together, including causing said bonding regions to react with said semiconductor regions.
18. A process for manufacturing an integrated device, comprising: forming integrated structures in a first wafer of semiconductor material, the first wafer having a face; forming interconnection structures of conductor material on a face of a second wafer of semiconductor material, including forming plug elements each having a bonding region of a metal material capable of reacting with said semiconductor material of said first wafer; forming self-alignment structures on the respective faces of said first and second wafers, and aligning said first and second wafers in a face-to-face configuration, using said self-alignment structures; and bonding said first wafer and said second wafer together, including causing said bonding regions to react with said semiconductor material of said first wafer.
19. A process for manufacturing an integrated device, comprising: forming a structure in a first wafer of semiconductor material, including a movable component; forming an integrated electronic component in a second wafer of semiconductor material; forming a bonding layer, including a base region and a bonding region of a metal material on a selected one of the first or second wafer; and bonding the first and second wafers together by causing the bonding region of the bonding layer to react with an exposed semiconductor material region on the one of the first or second wafers not selected.
20. A process for manufacturing an integrated device, comprising: forming an integrated structure in a first wafer of semiconductor material; forming a through connection region in a second wafer of semiconductor material; forming a bonding layer, including a base region and a bonding region of a metal material on a selected one of the first or second wafer; and bonding the first and second wafers together by causing the bonding region of the bonding layer to react with an exposed semiconductor material region on the one of the first or second wafers not selected.
21. The process of claim 20 , further comprising forming an annular insulation region isolating the through connection region within the second wafer of semiconductor material.
22. The process of claim 20 , further comprising: forming a plurality of through connection regions, wherein the forming a through connection region step is comprised in the present step; and forming a plurality of annular insulation regions, each isolating one of the plurality of through connection regions.
23. A process for manufacturing an integrated device, comprising: forming a first wafer including semiconductor regions and isolation regions; forming a second wafer including interconnection structures of conductor material; forming, on the second wafer, plug elements, each including a base region and a bonding region, the bonding region of a metal material different from the base region and capable of reacting with said semiconductor regions of said first wafer; and bonding said first wafer and said second wafer together, including causing said bonding regions to react with said semiconductor regions.
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December 19, 2001
January 11, 2005
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