A semiconductor device is provided with a semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film and having a portion increasing upward in the length along a gate length direction, a side wall formed on a side surface of the gate electrode so as to be covered behind a top part of the gate electrode as seen in plan view, and an interlayer insulation film covering the gate electrode. The side wall is in contact with the interlayer insulation film.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of fabricating a semiconductor device comprising the steps of: forming first, second and third insulation films on a semiconductor substrate in succession; forming an opening in said third insulation film; forming an opening of tapered shape, narrowing with depth, in said second insulation film under a bottom of said opening in said third insulation film; forming an opening in said first insulation film consistent with a bottom shape of said opening in said second insulation film, and depositing a gate oxide film entirely therein; burying a conductive film into said openings formed in said first, second and third insulation films to form a gate electrode; planarizing a surface of said conductive film and said third insulation film; and etching said first, second and third insulation films with said conductive film used as a mask to form a side wall on a side surface of said gate electrode so as to be covered behind a top part of said gate electrode as seen in plain view.
2. The method of fabricating a semiconductor device according to claim 1 , wherein said step of planarizing a surface is carried out by applying a chemical mechanical polishing to said surface.
3. The method of fabricating a semiconductor device according to claim 1 , further comprising the steps of: implanting ions into a surface of said semiconductor substrate with said conductive film used as a mask to form a diffusion layer; forming an interlayer insulation film covering said conductive film and diffusion layer; and forming a common contact hole reaching said conductive film and said diffusion layer in said interlayer insulation film, a part of said common contact hole reaching said common conductive film and said diffusion layer.
4. The method of fabricating a semiconductor device according to claim 2 , further comprising the steps of: implanting ions into a surface of said semiconductor substrate with said conductive film used as a mask to form a diffusion layer; forming an interlayer insulation film covering said conductive film and said diffusion layer; and forming a common contact hole reaching said conductive film and said diffusion layer in said interlayer insulation film, a part of said common contact hole reaching said common conductive film and said diffusion layer.
5. A method of fabricating a semiconductor device comprising the steps of: forming first, second and third insulation films on a semiconductor substrate in succession; forming an opening in said third insulation film; forming an opening of tapered shape, narrowing with depth, in said second insulation film under a bottom of said opening in said third insulation film; forming an opening in said first insulation film consistent with a bottom shape of said opening in said second insulation film, and depositing a gate oxide film only in said opening in said first insulation film; burying a conductive film into said openings formed in said first, second and third insulation films to form a gate electrode; planarizing a surface of said conductive film and said third insulation film; and etching said first, second and third insulation films with said conductive film used as a mask to form a side wall on a side surface of said gate electrode so as to be covered behind a top part of said gate electrode as seen in plain view.
6. The method of fabricating a semiconductor device according to claim 5 , wherein said step of planarizing a surface is carried out by applying a chemical mechanical polishing to said surface.
7. The method of fabricating a semiconductor device according to claim 5 , further comprising the steps of: implanting ions into a surface of said semiconductor substrate with said conductive film used as a mask to form a diffusion layer; forming an interlayer insulation film covering said conductive film and diffusion layer; and forming a contact hole reaching said conductive film and said diffusion layer in said interlayer insulation film, a part of said contact hole reaching said common conductive film and said diffusion layer.
8. The method of fabricating a semiconductor device according to claim 5 , further comprising the steps of: implanting ions into a surface of said semiconductor substrate with said conductive film used as a mask to form a diffusion layer; forming an interlayer insulation film covering said conductive film and said diffusion layer; and forming a common contact hole reaching said conductive film and said diffusion layer in said interlayer insulation film, a part of said contact hole reaching said common conductive film and said diffusion layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 9, 2003
January 11, 2005
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