A composite SOI semiconductor wafer (1) comprises a device layer (2) and a handle layer (3) with a buried oxide layer (4) located between the device and handle layers (2,3). The device and handle layers (2,3) are formed from device and handle wafers (9,10), respectively. A peripheral ridge (14) extending around a first major surface (12) of the device wafer (9) adjacent the peripheral edge (16) thereof is removed by etching a peripheral recess (25) to a depth (d) into the device wafer (9) prior to bonding the device and handle wafers (9,10), in order to avoid an unbonded peripheral pardon extending around the composite wafer (1). The depth to which the peripheral recess (25) is etched is greater then the final finished thickness t of the device layer (2). An oxide layer (22) is grown on the device water (9) and a photoresist layer (23) on the oxide layer (22) is patterned to define the peripheral recess (25). The oxide layer (22) is etched leaving only a portion of the oxide layer (22) beneath the photoresist layer (23), which subsequently forms the oxide layer (4). The peripheral recess (25) is then etched, and the photoresist layer (23) is removed. The oxide layer (22) is fusion bonded to a first major surface (18) of the handle wafer (10) by a high temperature bond anneal. Thereafter the device layer (2) is machined to its final finished thickness t.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for forming a composite semiconductor wafer in the form of a laminate from first and second wafers of semiconductor material, the method comprising the step of forming a peripheral recess in a first major surface of the first wafer adjacent a peripheral edge thereof corresponding to respective peripheral areas of the first major surfaces of the first and second wafers where a surface imperfection may occur go that the surface imperfection does not interfere with the formation of the laminate of the first and second wafers with the first major surface of the respective first and second wafers facing in directions towards each other.
2. A method as claimed in claim 1 in which the peripheral recess is formed into the first wafer to a depth from the first major surface which is at least equal to the thickness to which the first wafer is to be subsequently finished after the laminate of the first and second wafers has been formed so that at least a portion of the periphery of the finished first wafer is defined by the peripheral recess.
3. A method as claimed in claim 2 in which the peripheral recess is formed into the first wafer to a depth from the first major surface which is greater than the thickness to which the first wafer is to be subsequently finished after the formation of the laminate of the first and second wafers.
4. A method as claimed in claim 1 in which at least one layer of material is formed on the first major surface of at least one of the first and second wafers to form a buried layer between the first major surfaces of the first and second wafers when the laminate of the first and second wafers has been formed.
5. A method as claimed in claim 4 in which each layer which is to form the buried layer is an oxide layer.
6. A method as claimed in claim 4 in which each layer which is to form the buried layer is a grown layer.
7. A method as claimed in claim 4 in which each layer which is to form the buried layer is a deposited layer.
8. A method as claimed in claim 4 in which the layer which is to form the buried layer is formed on the first wafer.
9. A method as claimed in claim 4 in which the layer which is to form the buried layer is formed on the second wafer.
10. A method as claimed in claim 4 in which the layer which is to form the buried layer is formed on the first wafer subsequent to the formation of the peripheral recess.
11. A method as claimed in claim 4 in which the layer which is to form the buried layer is formed on the first wafer prior to the formation of the peripheral recess, and the peripheral recess is formed through the said layer.
12. A method an claimed in claim 1 in which the peripheral recess is formed by etching the first wafer through the first major surface thereof.
13. A method as claimed in claim 12 in which the peripheral recess is formed by wet etching.
14. A method as claimed in claim 12 in which the peripheral recess is formed by dry etching.
15. A method as claimed in claim 12 in which the peripheral recess is etched through a patterned layer formed on the first major surface defining the peripheral recess.
16. A method as claimed in claim 1 in which the peripheral recess is formed by machining.
17. A method as claimed in claim 1 in which the surface imperfection is on the first major surface of the first wafer.
18. A method as claimed in claim 1 in which the surface imperfection comprises a ridge extending from and around the first major surface adjacent the peripheral edge thereof.
19. A method as claimed in claim 1 in which the first major surface of the first wafer is a polished surface, and the surface imperfection results from the polishing process.
20. A method as claimed in claim 1 in which the first major surface of the second wafer is a polished surface, and the surface imperfection results from the polishing process.
21. A method as claimed in claim 20 in which a protective layer is formed on the polished surface of at least one of the first and second wafers.
22. A method as claimed in claim 1 in which the peripheral recess is formed to extend completely around the first wafer.
23. A method as claimed in claim 1 in which the material of the first wafer is silicon.
24. A method as claimed in claim 1 in which the material of the second wafer is silicon.
25. A method as claimed in claim 1 in which the first wafer is machined to a desired thickness after the laminate of the first and second wafers has been formed, the desired thickness being not greater than the depth to which the peripheral recess is etched into the first wafer from the first major surface thereof.
26. A method as claimed in claim 1 in which the second wafer is provided to form a handle layer of the composite wafer, and the first wafer is provided to form a device layer of the composite wafer in which devices are formed subsequent to the forming of the laminate of the first and second wafers.
27. A method as claimed in claim 25 in which the devices are micro-mechanical devices.
28. A method as claimed in claim 25 in which the devices are electronic devices.
29. A composite semiconductor wafer in the form of a laminate comprising: a first wafer of semiconductor material having a first major surface, and a second wafer of semiconductor material having a first major surface, the first major surface of the second wafer facing in a direction towards the first major surface of the first wafer, wherein at least a portion of the periphery of the first wafer is defined by a peripheral recess, which had been formed in the first wafer through the first major surface adjacent a peripheral edge thereof prior to the laminate of the first and second wafers being formed, so that any surface imperfection on the first major surfaces of the first and second wafers in the area corresponding to the area where the peripheral recess had been formed does not interfere with the formation of the laminate of the first and second wafers.
30. A composite semiconductor wafer as claimed in claim 29 in which the thickness to which the first wafer is finished after the formation of the laminate of the first and second wafers does not exceed the depth to which the peripheral recess had been formed into the first wafer through the first major surface thereof so that at least a portion of the periphery of the finished first wafer is defined by the peripheral recess.
31. A composite semiconductor wafer as claimed in claim 29 in which at least one buried layer is located between the first major surfaces of the first and second wafers.
32. A composite semiconductor wafer as claimed in claim 31 in which the buried layer is an oxide layer.
33. A composite semiconductor wafer as claimed in claim 31 in which the area of the buried layer is similar to the area of the first major surface of the first wafer defined by the peripheral recess so that the peripheral edge of the first wafer defined by the peripheral recess and the adjacent peripheral edge of the buried layer coincide.
34. A composite semiconductor wafer as claimed in claim 29 in which the semiconductor material of at least one of the first and second wafers is silicon.
35. A composite semiconductor wafer as claimed in claim 29 in which a component is formed in one of the first and second wafers.
36. A composite semiconductor wafer as claimed in claim 35 in which the component is a micro-mechanical component.
37. A composite semiconductor wafer as claimed in claim 35 in which the component is an electronic device.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 6, 2003
January 11, 2005
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