There is disclosed a semiconductor integrated circuit in which an equalize circuit is connected between input nodes N1, bN1 of a differential sense amplifier. A latch circuit is connected between nodes N2, bN2. A data change circuit is connected between the nodes N1 and bN2 and between the nodes bN1 and N2. A disconnection circuit is connected between the nodes N1 and N2 and between the nodes bN1 and bN2. In a state in which potentials of the input nodes N1, bN1 are equal to each other, the differential sense amplifier is operated, and output data of the amplifier is reversed by the data change circuit and subsequently latched by the latch circuit. The latched data is supplied to the input nodes N1, bN1 of the differential sense amplifier.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor integrated circuit comprising: an inner circuit; a first circuit which supplies a first signal for obtaining output data dependent on a state of said inner circuit to said inner circuit; a latch circuit which latches said output data; and a second circuit which supplies a second signal for returning the state of said inner circuit to a normal state based on said output data to said inner circuit.
2. A semiconductor integrated circuit according to claim 1 , wherein said output data and second signal are binary data, and said second signal has a value reverse to the value of said output data.
3. A semiconductor integrated circuit comprising: a first circuit which supplies a first signal for obtaining output data dependent on a mismatch of a threshold voltage of a MOS transistor to said MOS transistor; a latch circuit which latches said output data; and a second circuit which supplies a second signal for eliminating the mismatch of the threshold voltage of said MOS transistor based on said output data to said MOS transistor.
4. A semiconductor integrated circuit according to claim 3 , wherein said output data and second signal are binary data, and said second signal has a value reverse to the value of said output data.
5. A semiconductor integrated circuit comprising: a sense amplifier connected between first and second nodes; an equalize circuit which equalizes potentials of said first and second nodes; a latch circuit connected between third and fourth nodes; a data change circuit which controls electric connection or disconnection of said first and fourth nodes and electric connection or disconnection of said second and third nodes; and a disconnection circuit which controls electric disconnection or connection of said first and third nodes and electric disconnection or connection of said second and fourth nodes.
6. A semiconductor integrated circuit according to claim 5 , further comprising: a memory cell array including a plurality of memory cells, wherein said latch circuit is one of said plurality of memory cells.
7. A semiconductor integrated circuit according to claim 5 , wherein said data change circuit includes a MOS transistor connected between said first and fourth nodes, and a MOS transistor connected between said second and third nodes.
8. A semiconductor integrated circuit according to claim 5 , wherein said disconnection circuit includes a MOS transistor connected between said first and third nodes, and a MOS transistor connected between said second and fourth nodes.
9. A semiconductor integrated circuit according to claim 5 , wherein said disconnection circuit electrically disconnects said first and third nodes and said second and fourth nodes, when said sense amplifier is in an operative state, and electrically connects said first and third nodes and said second and fourth nodes, when said sense amplifier is in an inoperative state.
10. A semiconductor integrated circuit according to claim 5 , wherein said latch circuit latches data having a value reverse to a value of output data of said sense amplifier obtained when the potentials of said first and second nodes are equalized.
11. A semiconductor integrated circuit according to claim 10 , wherein the data having the value reverse to the value of the output data of said sense amplifier is generated by said data change circuit.
12. A semiconductor integrated circuit according to claim 11 , wherein the data having the value reverse to the value of the output data of said sense amplifier is given to said sense amplifier from said latch circuit.
13. A semiconductor integrated circuit according to claim 5 , wherein said latch circuit latches output data of said sense amplifier obtained when the potentials of said first and second nodes are equalized.
14. A semiconductor integrated circuit according to claim 13 , wherein said data change circuit generates data having a value reverse to a value of the output data of said sense amplifier.
15. A semiconductor integrated circuit according to claim 14 , wherein the data having the value reverse to the value of the output data of said sense amplifier is given to said sense amplifier from said data change circuit.
16. A semiconductor integrated circuit according to claim 5 , further comprising: means for bringing said sense amplifier into an operative state in a state in which the potentials of said first and second nodes are equalized and for outputting output data from said sense amplifier; means for using said data change circuit to generate data having a value reverse to a value of said output data; means for allowing said latch circuit to latch the data having the value reverse to the value of said output data; means for allowing said latch circuit to transfer the data having the value reverse to the value of said output data to said sense amplifier; and means for bringing said sense amplifier into the operative state.
17. A semiconductor integrated circuit according to claim 5 , wherein said sense amplifier includes a MOS transistor formed on a SOI substrate.
18. A semiconductor integrated circuit comprising: a sense amplifier connected between first and second nodes; an equalize circuit which equalizes potentials of said first and second nodes; a latch circuit connected between third and fourth nodes; a data change circuit which controls electric connection or disconnection of said first node and a first inner node of said latch circuit and electric connection or disconnection of said second node and a second inner node of said latch circuit; and a disconnection circuit which controls electric disconnection or connection of said first and third nodes and electric disconnection or connection of said second and fourth nodes.
19. A semiconductor integrated circuit according to claim 18 , further comprising: a memory cell array including a plurality of memory cells, wherein said latch circuit latches readout data read out of said plurality of memory cells.
20. A semiconductor integrated circuit according to claim 18 , wherein said data change circuit includes a MOS transistor connected between said first node and first inner node, and a MOS transistor connected between said second node and second inner node.
21. A semiconductor integrated circuit according to claim 18 , wherein said disconnection circuit includes a MOS transistor connected between said first and third nodes, and a MOS transistor connected between said second and fourth nodes.
22. A semiconductor integrated circuit according to claim 18 , wherein said disconnection circuit electrically disconnects said first and third nodes and said second and fourth nodes, when said sense amplifier is in an operative state, and electrically connects said first and third nodes and said second and fourth nodes, when said sense amplifier is in an inoperative state.
23. A semiconductor integrated circuit according to claim 18 , wherein said latch circuit latches data having a value reverse to a value of output data of said sense amplifier obtained when the potentials of said first and second nodes are equalized.
24. A semiconductor integrated circuit according to claim 23 , wherein the data having the value reverse to the value of the output data of said sense amplifier is generated by said data change circuit.
25. A semiconductor integrated circuit according to claim 24 , wherein the data having the value reverse to the value of the output data of said sense amplifier is given to said sense amplifier from said latch circuit.
26. A semiconductor integrated circuit according to claim 18 , wherein said latch circuit latches output data of said sense amplifier obtained when the potentials of said first and second nodes are equalized.
27. A semiconductor integrated circuit according to claim 26 , wherein said data change circuit generates data having a value reverse to a value of the output data of said sense amplifier.
28. A semiconductor integrated circuit according to claim 27 , wherein the data having the value reverse to the value of the output data of said sense amplifier is given to said sense amplifier from said data change circuit.
29. A semiconductor integrated circuit according to claim 18 , further comprising: means for bringing said sense amplifier into an operative state in a state in which the potentials of said first and second nodes are equalized and for outputting output data from said sense amplifier; means for using said data change circuit to generate data having a value reverse to a value of said output data and for allowing said latch circuit to latch the data; means for allowing said latch circuit to transfer the data having the value reverse to the value of said output data to said sense amplifier; and means for bringing said sense amplifier into the operative state.
30. A semiconductor integrated circuit according to claim 18 , wherein said sense amplifier includes a MOS transistor formed on a SOI substrate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 26, 2002
January 18, 2005
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