A nonvolatile ferroelectric memory device includes a plurality of top array blocks disposed along a first direction, each having a plurality of top sub-cell array blocks disposed along a second direction perpendicular to the first direction, each of the top sub-cell array blocks include a first plurality of unit cells, a plurality of bottom array blocks disposed along the first direction below the plurality of top array blocks, each having a plurality of bottom sub-cell array blocks disposed along the second direction, each of the bottom sub-cell array blocks include a second plurality of unit cells, a plurality of sub-bit lines extending along the second direction and disposed at equal first intervals along the first direction, each sub-bit line connected to at least a first end of one of the first and second pluralities of unit cells, and a plurality of main bit lines extending along the second direction and disposed at the equal first intervals along a third direction perpendicular to both the first and second directions.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A nonvolatile ferroelectric memory device, comprising: a plurality of top array blocks disposed along a first direction, each having a plurality of top sub-cell array blocks disposed along a second direction perpendicular to the first direction, each of the top sub-cell array blocks including a first plurality of unit cells; a plurality of bottom array blocks disposed along the first direction below the plurality of top array blocks, each having a plurality of bottom sub-cell array blocks disposed along the second direction, each of the bottom sub-cell array blocks including a second plurality of unit cells; a plurality of sub-bit lines extending along the second direction and disposed at equal first intervals along the first direction, each sub-bit line connected to at least a first end of one of the first and second pluralities of unit cells; and a plurality of main bit lines extending along the second direction and disposed at the equal first intervals along a third direction perpendicular to both the first and second directions, said main bit lines being formed in a plurality of layers that are disposed on a plurality of parallel planes.
2. The device according to claim 1 , wherein each of the main bit lines are disposed at equal second intervals along the first direction.
3. The device according to claim 1 , wherein the main bit lines are disposed on at least three parallel planes.
4. The device according to claim 2 , wherein the sub-bit lines are disposed at the equal second intervals along the first direction.
5. The device according to claim 1 , wherein the sub-bit lines are disposed at the equal second intervals along the third direction.
6. The device according to claim 5 , wherein the sub-bit lines are disposed on a plurality of parallel planes.
7. The device according to claim 6 , wherein the sub-bit lines are disposed on at least three parallel planes.
8. The device according to claim 1 , wherein each of the main bit lines directly overlies one of the sub-bit lines.
9. The device according to claim 1 , further comprising a plurality of metal lines alternatingly disposed on at least one of said plurality of main bit line layers between main bit lines of said at least one layer.
10. The device according to claim 9 , wherein the metal lines are electrically grounded.
11. The device according to claim 1 , wherein each cell array block comprises: a plurality of pairs of split word lines connected to each of the sub-bit lines; a first plurality and a second plurality of supply lines extending along the second direction and connected to each of the top and bottom sub-cell array blocks; and a plurality of switching control blocks driven by the supply lines.
12. The device according to claim 11 , wherein each switching control block comprises: a first transistor having a gate connected to one of the first plurality of supply lines, a first source/drain connected to one of the sub-bit lines, and a second source/drain connected to a power supply; and a second transistor having a gate connected to one of the second plurality of supply lines, a third source/drain connected to the first source/drain of the first transistor, and a fourth source/drain connected to one of the plurality of main bit lines.
13. The device according to claim 11 , wherein each switching control block comprises: a first transistor having a gate connected to one of the first plurality of supply lines, a first source/drain connected to one of the sub-bit lines, and a second source/drain connected to a power supply; a second transistor having a gate connected to one of the second plurality of supply lines, a third source/drain connected to the first source/drain of the first transistor, and a fourth source/drain connected to one of the plurality of main bit lines; and a third transistor having a gate connected to one of a third plurality of supply lines extending along the second direction SBPU supply line, a fifth source/drain connected to the third source/ drain of the second transistor and the first source/drain of the first transistor, and a sixth source/drain connected to electrical ground.
14. The device according to claim 1 , wherein each of the top and bottom array blocks include a plurality of word line and plate line pairs extending along the second direction, and a plurality of switching control blocks enabled by a bit line switching supply line and electrically interconnected between one of the plurality of sub-bit lines and one of the plurality of main bit lines.
15. A method of fabricating a nonvolatile ferroelectric memory device, comprising steps of: forming a plurality of top array blocks disposed along a first direction, each having a plurality of top sub-cell array blocks disposed along a second direction perpendicular to the first direction, each of the top sub-cell array blocks including a first plurality of unit cells; forming a plurality of bottom array blocks disposed along the first direction below the plurality of top array blocks, each having a plurality of bottom sub-cell array blocks disposed along the second direction, each of the bottom sub-cell array blocks including a second plurality of unit cells; forming a plurality of sub-bit lines extending along the second direction and disposed at equal first intervals along the first direction, each sub-bit line connected to at least a first end of one of the first and second pluralities of unit cells; and forming a plurality of main bit lines extending along the second direction and disposed at the equal first intervals along a third direction perpendicular to both the first and second directions, said main bit lines being formed in a plurality of layers that are disposed on a plurality of parallel planes.
16. The method according to claim 15 , wherein each of the main bit lines are formed at equal second intervals along the first direction.
17. The method according to claim 15 , wherein the main bit lines are formed on at least three parallel planes.
18. The method according to claim 16 , wherein the sub-bit lines are formed at the equal second intervals along the first direction.
19. The method according to claim 15 , wherein the sub-bit lines are formed at the equal second intervals along the third direction.
20. The method according to claim 19 , wherein the sub-bit lines are formed on a plurality of parallel planes.
21. The method according to claim 20 , wherein the sub-bit lines are formed on at least three parallel planes.
22. The method according to claim 15 , wherein each of the main bit lines are formed to directly overlie one of the sub-bit lines.
23. The method according to claim 15 , further comprising the step of forming a plurality of metal lines between the plurality of main bit lines.
24. A nonvolatile ferroelectric memory device, comprising: a plurality of top array blocks disposed along a first direction, each having a plurality of top sub-cell array blocks disposed along a second direction perpendicular to the first direction, each of the top sub-cell array blocks including a first plurality of unit cells; a plurality of bottom array blocks disposed along the first direction below the plurality of top array blocks, each having a plurality of bottom sub-cell array blocks disposed along the second direction, each of the bottom sub-cell array blocks including a second plurality of unit cells; a plurality of sub-bit lines extending along the second direction and disposed at equal first intervals along the first direction, each sub-bit line connected to at least a first end of one of the first and second pluralities of unit cells; a plurality of main bit lines extending along the second direction and disposed at the equal first intervals along a third direction perpendicular to both the first and second directions; each cell array block including, a plurality of pairs of split word lines connected to each of the sub-bit lines; a first plurality and a second plurality of supply lines extending along the second direction and connected to each of the top and bottom sub-cell array blocks; and a plurality of switching control blocks driven by the supply lines, each switching control block including, a first transistor having a gate connected to one of the first plurality of supply lines, a first source/drain connected to one of the sub-bit lines, and a second source/drain connected to a power supply; and a second transistor having a gate connected to one of the second plurality of supply lines, a third source/drain connected to the first source/drain of the first transistor, and a fourth source/drain connected to one of the plurality of main bit lines.
25. A method of fabricating a nonvolatile ferroelectric memory device, comprising steps of: forming a plurality of top array blocks disposed along a first direction, each having a plurality of top sub-cell array blocks disposed along a second direction perpendicular to the first direction, each of the top sub-cell array blocks including a first plurality of unit cells; forming a plurality of bottom array blocks disposed along the first direction below the plurality of top array blocks, each having a plurality of bottom sub-cell array blocks disposed along the second direction, each of the bottom sub-cell array blocks including a second plurality of unit cells; forming a plurality of sub-bit lines extending along the second direction and disposed at equal first intervals along the first direction, each sub-bit line connected to at least a first end of one of the first and second pluralities of unit cells; forming a plurality of main bit lines extending along the second direction and disposed at the equal first intervals along a third direction perpendicular to both the first and second directions; and forming a plurality of metal lines between the plurality of main bit lines.
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December 3, 2002
January 18, 2005
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