Program counting circuit and program word line voltage generating circuit in flash memory device using the same

1. A program counting circuit, comprising: a data transmit unit having a plurality of fuses for receiving and transferring data; a counting reset unit for generating a reset signal in order to set the data transferred from the data transmit unit to an initial counting value; and a counting unit for setting the data to the initial counting value depending on the reset signal and sequentially performing a counting operation from the initial counting value set by A clock signal.

2. The program counting circuit as claimed in claim 1 , wherein the data transmit unit comprises: a plurality of PMOS transistors for transferring the power supply voltage to one end of each of the plurality of the fuses, respectively; and a plurality of NMOS transistors for transferring the ground voltage to the other end of each of the plurality of the fuses, respectively.

3. The program counting circuit as claimed in claim 2 , wherein the plurality of the PMOS transistors have channels longer than those of the plurality of the NMOS transistors.

4. The program counting circuit as claimed in claim 1 , wherein the data is a power supply voltage or a ground voltage.

5. The program counting circuit as claimed in claim 1 , wherein the plurality of the fuses are poly lines formed when semiconductor devices are fabricated.

6. The program counting circuit as claimed in claim 1 , wherein the counting unit includes a plurality of flip-flops.

7. The program counting circuit as claimed in claim 6 , wherein the plurality of the flip-flops comprises: a setting unit for transferring the data to a node depending on the reset signal; a first output unit for outputting the data transferred to the node; an inverter for inverting an output signal of the first output unit; a transmit unit for transferring an output signal of the inverter to the node depending on a control signal and the clock signal; and a second output unit for logically combining an output signal of the first output unit and the control signal.

8. The program counting circuit as claimed in claim 7 , wherein the setting unit includes a transfer gate that is driven by the reset signal to transfer the date to the node.

9. The program counting circuit as claimed in claim 7 , wherein the first output unit comprises: a first latch for latching the data of the node; a transfer gate driven by the clock signal and an inverted signal of the clock signal to transfer the output signal of the first latch; and a second latch for latching an output signal of the transfer gate.

10. The program counting circuit as claimed in claim 7 , wherein the transmit unit comprises: a first transfer gate driven by the control signal to transfer the output signal of the inverter; and a second transfer gate driven by the clock signal to transfer an output signal of the first transfer gate to the node.

11. The program counting circuit as claimed in claim 7 , wherein the control signal is the ground voltage or an output signal of the second output unit of the flip-flop connected to at a front stage.

12. A program word line voltage generating circuit, comprising: the program counting circuit of claim 1 ; a decoding circuit unit for decoding an output signal of the program counting circuit unit; and a high-voltage generating circuit unit for generating a high voltage depending on the output signal of the decoding circuit unit.

13. The program word line voltage generating circuit as claimed in claim 12 , wherein the decoding circuit unit comprises: an input inverse unit for inverting the output signal of the program counting circuit; and a decoding output unit for logically combining the output signal of the program counting circuit and an output signal of the input inverse unit.

14. The program word line voltage generating circuit as claimed in claim 13 , wherein the decoding output unit comprises: a plurality of NOR gates for logically combining the output signal of the program counting circuit and the output signal of the input inverse unit; a flip-flop for latching an output signal of any one of the plurality of the NOR gates and a program enable signal; and an inverter for inverting an output signal of the flip-flop to transfer the inverted signal to input terminals of the plurality of the NOR gates.

15. The program word line voltage generating circuit as claimed in claim 14 , wherein the flip-flop is a R-S flip-flop.

16. The program word line voltage generating circuit as claimed in claim 12 , wherein the high-voltage generating circuit unit comprises: a voltage dividing unit for dividing a voltage depending on the output signal of the decoding circuit unit; a reference voltage generator for generating a reference voltage; a voltage comparing unit for comparing a divided voltage divided through the voltage dividing unit and the reference voltage; and a boosting circuit unit for generating a high voltage depending on an output signal of the voltage comparing unit.

17. The program word line voltage generating circuit as claimed in claim 16 , wherein the voltage dividing unit comprises: a plurality of NMOS transistor driven by the output signal of the decoding circuit unit; and a plurality of resistors for dividing a voltage depending on an operating state of the NMOS transistor.

18. The program word line voltage generating circuit as claimed in claim 17 , wherein the plurality of the resistors have different resistance values.