A graphics memory architecture in which row addresses are permuted, in a basically tile-oriented storage architecture, so that fast parallel access is provided both by scanlines (for video operations) and also by tiles (for graphics operations).
Legal claims defining the scope of protection, as filed with the USPTO.
1. A graphics processor for storing picture data, comprising: a plurality of tiles, each including data for a multi-row patch of spatially adjacent pixels; and a graphics controller comprising: memory access logic having at least two different modes of operation, wherein in a first mode of operation, said logic provides paralleled access to all rows of at least one selected tile, and in a second mode of operation, said logic provides paralleled access to at least one selected row of multiple tiles.
2. The graphics processor of claim 1 , wherein said tiles each include less than all bits of data for all pixels in a patch.
3. The graphics processor of claim 1 , wherein at least some ones of said tiles have different respective row-address-bit permutations.
4. A graphics processing method, comprising the steps of: storing computer graphics data in a tile format; and accessing said data in either of two modes, wherein in a first selectable mode of operation, all rows of at least one selected tile are accessed in parallel, and in a second selectable mode of operation, rows having the same position in multiple tiles are accessed in parallels; wherein said accessing step of accessing in either of two modes is performed by a graphics controller having memory access logic.
5. The graphics processing method of claim 4 , wherein said tiles each include less than all bits of data for all pixels in a patch.
6. The graphics processing method of claim 4 , wherein at least some ones of said tiles have different respective row-address-bit permutations.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 20, 2002
January 25, 2005
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