An interconnect module for an integrated circuit chip incorporates a thin, high dielectric constant embedded capacitor structure to provide reduced power distribution impedance, and thereby promote higher frequency operation. The interconnect module is capable of reliably attaching an integrated circuit chip to a printed wiring board via solder ball connections, while providing reduced power distribution impedance of less than or equal to approximately 0.60 ohms at operating frequencies in excess of 1.0 gigahertz.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An interconnect module comprising: a chip attach surface defining first contact pads for attachment to an integrated circuit chip; a board attach surface defining second contact pads for attachment to a printed wiring board; a capacitor structure having a first conductive layer, a second conductive layer, and a first dielectric layer formed between the first and second conductive layers, wherein the first conductive layer, the second conductive layer, and the first dielectric layer are laminated together; and conductive paths, formed in the interconnect module, that interconnect a plurality of the first contact pads to the first conductive layer, wherein the first contact pads, the conductive paths, and the capacitor structure produce a combined impedance of less than or equal to approximately 0.60 ohms at a frequency of greater than or equal to approximately 1.0 gigahertz.
2. The interconnect module of claim 1 , further comprising additional conductive layers and additional dielectric layers: a second dielectric layer formed between the first conductive layer and the chip attach surface; a third conductive layer formed between the second dielectric layer and the chip attach surface; a third dielectric layer formed between the second conductive layer and the board attach surface; and a fourth conductive layer formed between the third dielectric layer and the board attach surface.
3. The interconnect module of claim 2 , wherein said additional dielectric layers are formed from an expanded polytetrafluoroethylene matrix containing a mixed cyanate ester-epoxy adhesive and inorganic filler, and the layers of the interconnect module are laminated together to form a laminated package.
4. The interconnect module of claim 1 , wherein the conductive paths are coupled to vias that interconnect a plurality of the first contact pads with a corresponding plurality of the first and second conductive layers to distribute power from the first conductive layer and a ground potential from the second conductive layer.
5. The interconnect module of claim 1 , wherein the first and second conductive layers are copper foils, and the first dielectric layer is a coating of dielectric material formed on at least one of the copper foils.
6. The interconnect module of claim 5 , wherein the dielectric material comprises an epoxy resin loaded with dielectric particles.
7. The interconnect module of claim 6 , wherein the dielectric particles include barium titanate particles having an average particle size of approximately 0.2 microns.
8. The interconnect module of claim 5 , wherein each of the copper foils has an average surface roughness of approximately 8 nm on a side that receives the coating.
9. The interconnect module of claim 6 , wherein the epoxy resin is cured upon lamination of the first conductive layer, the second conductive layer, and the dielectric layer.
10. The interconnect module of claim 6 , wherein the dielectric particles are selected from the group consisting of barium titanate, barium strontium titanate, titanium oxide, and lead zirconium titanate.
11. The interconnect module of claim 1 , wherein the first dielectric layer has a thickness of less than or equal to approximately 8 microns, and a dielectric constant of at least about 12.
12. The interconnect module of claim 5 , wherein each of the copper foils has a thickness no greater than about 12 microns.
13. The interconnect module of claim 1 , wherein the capacitor structure has a thickness of less than or equal to approximately 32 microns, and a dielectric constant of at least about 12.
14. The interconnect module of claim 1 , wherein the chip attach surface defines an array of the first contact pads to which individual solder ball connections of the integrated circuit chip are connected.
15. The interconnect module of claim 2 , wherein the conductive paths include conductive vias that interconnect a plurality of the first contact pads with the third conductive layer, interconnect a plurality of the second contact pads with the fourth conductive layer, and interconnect the third and fourth conductive layers.
16. The interconnect module of claim 2 , wherein the first conductive layer is a power layer, the second conductive layer is a ground layer, and the third and fourth conductive layers are signal layers.
17. The interconnect module of claim 2 , further comprising: a first via to interconnect one or more of the first contact pads with the third conductive layer; and a second via to interconnect the third conductive layer with the first conductive layer, wherein the second via is offset from the first via, wherein the interconnect module defines an electrical signal path having a first portion in said third conductive layer routed in a direction toward the first conductive via, and a second portion in said first conductive layer routed in a direction toward the second conductive via, wherein said location of said second conductive via permits a mutual inductance formed by the first portion of the electrical signal path with the second portion of the electrical signal path to cancel a mutual inductance formed by the second portion of the electrical signal path with the first portion of the electrical signal path.
18. The interconnect module of claim 2 , comprising further additional conductive layers and additional dielectric layers wherein the additional dielectric layers are made of the same material, and have approximately the same thickness and the same thickness tolerance, and all of the layers are laminated to another to form the interconnect module.
19. The interconnect module of claim 18 , wherein the first conductive layer is a power layer, the second conductive layer is a ground layer, and the further additional conductive layers are signal layers.
20. The interconnect module of claim 1 , wherein the capacitor structure is a first capacitor structure, the interconnect module further comprising: a second capacitor structure having a third conductive layer, a fourth conductive layer, and a second dielectric layer formed between the third and fourth conductive layers; and a third dielectric layer formed between the first and second capacitor structures, wherein the conductive paths interconnect a plurality of the second contact pads to the fourth conductive layer.
21. The interconnect module of claim 20 , wherein each of the first and second dielectric layers has a thickness of less than or equal to approximately 8 microns, and a dielectric constant of at least about 12.
22. The interconnect module of claim 1 , wherein the capacitor structure is pre-tested for satisfactory electrical operation prior to incorporation in the interconnect module.
23. The interconnect module of claim 1 , further comprising: a semiconductor chip of the type having a plurality of individual solder ball connections on a mounting surface thereof; and wherein at least one lamina is formed by lamination of least two layers of the interconnect module, at least one dielectric layer and at least one conductive layer, at least one lamina comprising a dielectric layer being formed at least in part from polytetrafluoroethylene having disposed therein an inorganic filler material, wherein at least one via extends through said at least one lamina, said via having an entrance aperture in the conductive layer of less than 75 μm and an aspect ratio of between 3:1 and 25:1, and wherein the contact pads of the interconnect module are connected to the individual solder ball connections of said semiconductor chip.
24. The interconnect module of claim 1 , further comprising: an integrated circuit chip mounted on the chip attach surface of the interconnect module; and a lid having at least two regions exhibiting different coefficients of thermal expansion, wherein one of said regions has a coefficient of thermal expansion that substantially matches an in plane coefficient of thermal expansion of the integrated circuit chip, and wherein said other of said regions has a coefficient of thermal expansion that substantially matches an in plane coefficient of thermal expansion of said interconnect.
25. The interconnect module of claim 24 , wherein the lid is made of a metallic material disposed in a matrix material having at least one opening and further comprises a preform having at least two thicknesses, and an insert fitted into said at least one opening, wherein the insert is made of a second material having a different coefficient of thermal expansion.
26. The interconnect module of claim 24 , wherein the lid is connectable to the interconnect module through a constraining ring, and wherein a second region of the lid has a coefficient of thermal expansion that substantially matches an in plane coefficient of thermal expansion of the constraining ring.
27. The interconnect module of claim 25 , wherein the matrix material is silicon carbide and the metallic material is aluminum.
28. The interconnect module of claim 1 , further comprising a plurality of additional dielectric and conductive layers arranged in alternatingly disposed, vertically stacked dielectric and conductive layers about a plane of symmetry passing through the capacitor structure, wherein the additional dielectric layers include second and third dielectric layers disposed respectively on opposite sides of the capacitor structure, and the second and third dielectric layers are made of the same material, and have approximately the same thickness and the same thickness tolerance, wherein outer-most layers of the stack are conductive layers having substantially the same thickness, and the thickness of the outer-most conductive layers are thicker than any other conductive layers, wherein a plurality of said additional dielectric layers have a higher elastic modulus relative to said other dielectric layers, wherein said plurality of said dielectric layers having said higher elastic modulus are arranged outwardly, from said horizontal plane of symmetry, relative to said other dielectric layers such that the flexural modulus of said laminated substrate is substantially maximized.
29. The interconnect module of claim 3 , further comprising at least one additional conductive layer; and at least one additional dielectric layer bonded to the conductive layer, the dielectric layer having a glass transition temperature T g greater than 200° C. a volumetric coefficient of thermal expansion 75 ppm/° C., and wherein and the dielectric layer is an organic material having an inorganic filler material; and a chip electrically attached to the chip attach surface.
30. The interconnect module of claim 29 , wherein the at least one conductive layer and the at least one dielectric layer are bonded together so that the thickness of the resulting laminated substrate is between about 25 microns and about 750 microns.
31. The interconnect module of claim 30 , wherein the additional dielectric layer is selected from the group consisting of polyimides, polyimide laminates, epoxy resins, liquid crystal polymers and fluoropolymers.
32. The interconnect module of claim 1 , further comprising at least one via extending through at least an outermost dielectric layer of the interconnect module, each via having an entrance aperture and each respective entrance aperture having an entrance width no greater than about 75 μm, wherein at least one via is a through-via having an aspect ratio at least about 10:1 and an exit with a variance in width of about 10 μm 2 .
33. The interconnect module of claim 32 , wherein the outermost dielectric layer is a high-temperature organic dielectric substrate material selected from the group consisting of polyimides, epoxy resins, polytetrafluoroethylene, and liquid crystal polymer adhesive bonded to the interconnect module.
34. The interconnect module of claim 32 , wherein at least one via is a blind via having an aspect ratio equal to or greater than 1:1.
35. A method for forming an interconnect module, the method comprising: providing a laminated capacitor structure having a first conductive layer, a second conductive layer, and a dielectric layer formed between the first and second conductive layers and laminated into a unitary structure; forming a chip attach surface defining first contact pads for attachment of an integrated circuit chip to the interconnect module on a first side of the capacitor structure; forming a board attach surface defining second contact pads for attachment of the interconnect module to a printed wiring board on a second side of the capacitor structure; coupling the capacitor structure, the chip attach surface, and the board attach surface to form the interconnect module; and forming conductive paths that interconnect a plurality of the first contact pads to the first conductive layer, wherein the first contact pads, the conductive paths, and the capacitor structure produce a combined impedance of less than or equal to approximately 0.60 ohms at a frequency of greater than or equal to approximately 1.0 gigahertz.
36. The method of claim 35 , further comprising the steps of forming additional dielectric layers and additional conductive layers: forming a second dielectric layer between the first conductive layer and the chip attach surface; forming a third conductive layer between the second dielectric layer and the chip attach surface; forming a third dielectric layer between the second conductive layer and the board attach surface; and forming a fourth conductive layer between the third dielectric layer and the board attach surface.
37. The method of claim 36 , wherein the additional dielectric layers are formed from an expanded polytetrafluoroethylene matrix containing a mixed cyanate ester-epoxy adhesive and inorganic filler, the method further comprising laminating all of the layers together to form a laminated package.
38. The method of claim 36 , further comprising forming the conductive paths to include conductive vias that interconnect at least one of the first contact pads with the third conductive layer, interconnect a plurality of the second contact pads with the fourth conductive layer, and interconnect portions of the third and fourth conductive layers.
39. The method of claim 36 , wherein the first conductive layer is a power layer, the second conductive layer is a ground layer, and the additional conductive layers are signal layers.
40. The method of claim 35 , wherein the chip attach surface defines an array of the first contact pads to which individual solder ball connections of the integrated circuit chip are connected.
41. The method of claim 35 , wherein the conductive paths are formed to include vias that interconnect a plurality of the first contact pads with the first and second conductive layers to distribute power from the first conductive layer and a ground potential from the second conductive layer.
42. The method of claim 35 , further comprising laminating the first conductive layer, the second conductive layer, and the dielectric layer together before forming the interconnect module.
43. The method of claim 42 , wherein the first and second conductive layers are copper foils, and the first dielectric layer is a coating of dielectric material formed on at least one of the copper foils.
44. The method of claim 43 , wherein the dielectric material includes an epoxy resin loaded with dielectric particles selected from the group consisting of barium titanate, barium strontium titanate, titanium oxide, and lead zirconium titanate.
45. The method of claim 44 , wherein the dielectric particles include barium titanate particles having an average particle size of approximately 0.2 microns.
46. The method of claim 43 , wherein each of the copper foils has an average surface roughness of approximately 8 nm on a side that receives the coating.
47. The method of claim 44 , wherein the epoxy resin is cured during the lamination of the first conductive layer, the second conductive layer, and the first dielectric layer.
48. The method of claim 43 , wherein the first dielectric layer has a thickness of less than or equal to approximately 8 microns, and a dielectric constant of greater than or equal to approximately 12, each of the copper foils in the laminated capacitor structure has a thickness of from about 10 microns to about 40 microns.
49. The method of claim 36 , further comprising: forming a first conductive via selected from the group consisting of a blind via, a through-via and a buried via to interconnect one or more of the first conductive pads with the third conductive layer; forming a second conductive via selected from the group consisting of a blind via, a through-via and a buried via to interconnect the third conductive layer with the first conductive layer, wherein the second conductive via is offset from the first conductive via, and the interconnect module defines an electrical signal path having a first portion in said third conductive layer routed in a direction toward the first conductive via, and a second portion in said first conductive layer routed in a direction toward the second conductive via, wherein said location of said second conductive via permits a mutual inductance formed by the first portion of the electrical signal path with the second portion of the electrical signal path to cancel a mutual inductance formed by the second portion of the electrical signal path with the first portion of the electrical signal path.
50. The method of claim 36 , comprising providing further additional conductive and dielectric layers, laminating all of the provided layers together to form a laminated package, wherein further additional dielectric layers are made of the same material, and have approximately the same thickness and the same thickness tolerance.
51. The method of claim 36 , wherein the first conductive layer is a power layer, the second conductive layer is a ground layer, and any additional conductive layers are signal layers.
52. The method of claim 35 , wherein the capacitor structure is a first capacitor structure, the method further comprising: forming a second capacitor structure having a third conductive layer, a fourth conductive layer, and a second dielectric layer between the third and fourth conductive layers; and forming a third dielectric layer between the first and second capacitor structures, wherein the conductive paths interconnect a plurality of the first and second contact pads to the fourth conductive layer, wherein each of the first and second dielectric layers has a thickness of less than or equal to approximately 8 microns, and a dielectric constant of greater than or equal to approximately 12.
53. The method of claim 35 , further comprising the step of pre-testing the capacitor structure for satisfactory electrical operation prior to incorporation in the interconnect module.
54. The method of claim 36 , further comprising the steps of: forming a second dielectric layer on the first conductive layer; forming an exposed third conductive layer on the second dielectric layer, the third conductive layer having a preformed aperture; laser drilling through the second dielectric layer to the first conductive layer to form a blind via at a location within the preformed aperture of the third conductive layer using a plurality of laser pulses each having a first energy density per pulse, the first energy density per pulse being greater than an ablation threshold of the second dielectric layer and less than an ablation threshold of the first conductive layer; and laser drilling the first conductive layer for a predetermined number of pulses each having a second energy density per pulse, the second energy density being greater than an ablation threshold of the first conductive layer, the predetermined number of pulses causing a surface of the first conductive layer exposed by the laser drilling to become molten.
55. The method according to claim 54 , further comprising the step of filling the blind via with a conductive material.
56. The method according to claim 36 , wherein the third conductive layer has a plurality of preformed apertures, and the method further comprises the step of forming a plurality of blind vias by performing the step of laser drilling through the second dielectric layer to the first conductive layer to form a blind via at a location within at least two preformed apertures of the first conductive layer and the step of laser drilling the third conductive layer at each blind via in situ.
57. The method of claim 35 , further comprising: placing a first mask between an output optics of a laser and an exposed surface of a laminated interconnect module, the first mask having a first aperture corresponding to a location of a via in the interconnect module; placing a second mask between the first mask and the output optics of the laser, the second mask having a second aperture disposed within a main beam of a laser beam output from the laser, the second aperture blocking side lobes of the laser beam from reaching the exposed surface of the interconnect module; laser drilling a via in the interconnect module, applying a polymeric photo-absorptive layer on the exposed surface of the interconnect module; forming ablated material by laser drilling the via in the interconnect module through the photo-absorptive layer; redepositing the ablated material on the photo-absorptive layer surrounding the via; and enhancing an entrance of the via by removing the photo-absorptive layer and the ablated redeposited material on the photo-absorptive layer.
58. The method of claim 35 , further comprising: laser drilling a through-via in the interconnect from a top exposed surface of the interconnect to a bottom exposed surface of the interconnect using a plurality of laser pulses that are trepanned in a first predetermined pattern, each pulse trepanned in the first predetermined pattern having a first energy density per pulse; and laser drilling the through-via using a plurality of laser pulses that are trepanned in a second predetermined pattern, each pulse trepanned in the second predetermined pattern having a second energy density per pulse, the second energy density per pulse being greater than the first energy density per pulse, the second predetermined pattern being within the first predetermined pattern.
59. The method according to claim 58 , further comprising: applying a polymeric photo-absorptive layer on the exposed top surface of the interconnect before laser drilling the interconnect; forming ablated material by laser drilling the through-via in the interconnect through the photo-absorptive layer; redepositing the ablated material on the photo-absorptive layer surrounding the aperture; and enhancing an entrance of the through-via by removing the photo-absorptive layer and the ablated redeposited material on the photo-absorptive layer.
60. A method according to claim 36 , wherein the additional conductive layers are made of a material selected from the group consisting of copper, gold, silver and aluminum.
61. The method of claim 35 , further comprising: forming third and fourth conductive layers of the same type of material; patterning one of the third and fourth layers to form an electrical circuit pattern, thereby forming a patterned layer having a distribution of material; and altering the distribution of material in the other of the third and fourth conductive layers to match that of the patterned layer.
62. A method for making an interconnect module according to claim 35 comprising: laminated alternating conductive and dielectric layers about a central laminated capacitor structure; forming one or more blind vias through the conductive and dielectric layers; filling the blind vias with a conductive material to define conductive paths between the laminated capacitor structure and outer conductive layers of the interconnect module; plating the blind vias; and patterning the outer conductive layers to form contact pads over the blind vias, wherein the contact pads, the conductive paths, and the capacitor structure produce a combined power distribution impedance of less than or equal to approximately 0.60 ohms at a frequency of greater than or equal to approximately 1.0 gigahertz.
63. An interconnect module comprising: a laminated capacitor structure; alternating conductive and dielectric layers laminated to opposite sides of the capacitor structure; and one or more blind vias extending through the conductive and dielectric layers, wherein the blind vias are plated and filled with a conductive material to define conductive paths between the laminated capacitor structure and outer conductive layers of the interconnect module, and wherein the contact pads, the conductive paths, and the capacitor structure produce a combined power distribution impedance of less than or equal to approximately 0.60 ohms at a frequency of greater than or equal to approximately 1.0 gigahertz.
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July 19, 2002
January 25, 2005
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