A method of erasing non-volatile memory data. The erasing method includes applying a first voltage to a substrate, applying a second voltage to a control gate and setting both source terminal and drain terminal to a floating state during a first time interval so that F-N tunneling can be utilized to carry out an erasing operation. In a second time interval, the control gate voltage is changed from the first voltage applied to a third voltage. In a third time interval, the substrate voltage is changed from the second voltage to 0 volt to prevent over-erasure of the non-volatile memory. The second voltage and the first voltage are in reverse bias. Similarly, the third voltage and the first voltage are also in reverse bias.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of erasing non-volatile memory data, wherein the non-volatile memory at least includes a control gate, a substrate, a source region and a drain region, the method comprising the steps of: applying a first voltage to the substrate, applying a second voltage to the control gate and setting both the source and the drain region to a floating state in a first time interval so that Fowler-Nordheim tunneling is utilized to carry out the erasing operation; changing the first voltage applied to the control gate to a third voltage in a second time interval; and changing the second voltage applied to the substrate to 0 volt in a third time interval to prevent over-erasure of the non-volatile memory; wherein the second voltage and the first voltage are in reverse bias and the third voltage and the first voltage are in reverse bias.
2. The erasing method of claim 1 , wherein the step of changing the control gate voltage from the first voltage to the third voltage during the second time interval includes changing the control gate voltage from 0 volt to the third voltage after changing the control gate voltage from the first voltage to 0 volt.
3. The erasing method of claim 1 , wherein the step of changing the substrate voltage from the second voltage to 0 volt to prevent over-erasure includes changing the control gate voltage from the fourth voltage to 0 volt after changing the control gate voltage from the second voltage to a fourth voltage such that the fourth voltage has a value intermediate between the second voltage and 0 volt.
4. The erasing method of claim 1 , wherein the first voltage is between 9V to 15V.
5. The erasing method of claim 1 , wherein the second voltage is between 5V to 10V.
6. The erasing method of claim 1 , wherein the third voltage is between 0.1V to 5V.
7. A method of erasing non-volatile memory data, wherein the non-volatile memory at least includes a control gate, a substrate, a source region and a drain region, the method comprising the steps of: (a) applying a first voltage to the substrate, applying a second voltage to the control gate and setting both the source region and the drain region to a floating state and utilizing Fowler-Nordheim tunneling to carry out an erasing operation; (b) changing the voltage applied to the control gate from the first voltage to a third voltage; (c) changing the voltage applied to the substrate from the second voltage to 0 volt; and (d) repeating the steps from (a) to (c) until the erase threshold voltage of the non-volatile memory reaches a pre-defined value; wherein the second voltage and the first voltage are in reverse bias and the third voltage and the first voltage is in reverse bias.
8. The erasing method of claim 7 , wherein step (b) further includes the sub-steps of changing the control gate voltage from 0 volt to the third voltage after changing the control gate voltage from the first voltage to 0 volt.
9. The erasing method of claim 7 , wherein step (c) further includes the sub-steps of changing the substrate voltage from the fourth voltage to 0 volt after changing the substrate voltage from the second voltage to a fourth voltage such that the fourth voltage has a value intermediate between the second voltage and 0 volt.
10. The erasing method of claim 7 , wherein the first voltage is between 9V to 15V.
11. The erasing method of claim 7 , wherein the second voltage is between 5V to 10V.
12. The erasing method of claim 7 , wherein the third voltage is between 0.1V to 5V.
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January 24, 2003
January 25, 2005
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