A method for controlling the CMOS sensor array containing the first CMOS sensor cell, including the steps of receiving the clock signal and generating the first address; generating the reset signal to the first CMOS sensor cell based on the first address; calculating the read delay based on the first address and the offset value; and, generating the read address signal to the first CMOS sensor cell after the read delay. An apparatus for controlling a CMOS sensor array containing a first CMOS sensor cell, including a first logic circuit for receiving a clock signal and generating a first address; a second logic circuit coupled to the first logic circuit for receiving the first address and generating a reset signal to the first CMOS sensor cell based on the first address; a third logic circuit coupled to the first logic circuit for receiving the first address and calculating a read delay based on the first address and an offset value; and, a fourth logic circuit coupled to the first logic circuit for generating a read address signal to the first CMOS sensor cell after the read delay.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for controlling a sensor array containing a first group of sensor cells, comprising: receiving a clock signal and generating a first address value based on the clock signal; generating a reset signal to said first group of sensor cells based on said first address value; determining a delay value based on said first address value and and offset value; generating a read signal to said first group of sensor cells in accordance with said delay value; and then sampling a charge contained in each sensor cell in said first group; and changing an exposure time for the array by changing the offset value, wherein the offset value is an n bit binary number.
2. The method of claim 1 wherein said generating a reset signal includes generation of said reset signal to a second group of sensor cells based on said first address value.
3. The method of claim 1 wherein said generating a read signal includes generation of said read signal to a second group of sensor cells in accordance with said delay value.
4. The method of claim 1 wherein the determination of the delay value includes adding the offset value to the first address value.
5. The method of claim 4 wherein the generation of the read signal includes decoding the first address value to qualify the readout of only the first group in the array.
6. The method of claim 5 wherein the generation of the reset signal includes decoding the sum of (1) the offset value and (2) the first address value, to qualify the reset of only the first group of sensor cells in the array.
7. An apparatus for controlling a sensor array containing a first line of sensor cells arranged in a linear fashion, comprising: a first logic circuit for receiving a clock signal and to generate a first address, wherein said first logic circuit comprises an address generation circuit to provide said first address as a binary sequence whose value changes in response to each cycle of the clock signal and points to a line of sensor cells in the array, the binary sequence spans the entire sensor array in a single frame; a second logic circuit coupled to said first logic circuit to generate a line reset signal to said first line of sensor cells based on said first address; a third logic circuit coupled to said first logic circuit to receive said first address and to calculate a line read delay based on said first address and based on an offset value; and a fourth logic circuit coupled to said first logic circuit to generate a line read signal to said first line of sensor cells after said line read delay, to enable the sampling of a charge contained in each sensor cell in said first line of cells.
8. The apparatus of claim 7 , wherein said second logic circuit comprises a first address decoder.
9. The apparatus of claim 7 , wherein said third logic circuit comprises an adder.
10. The apparatus of claim 7 , wherein said fourth logic circuit comprises a second address decoder.
11. The apparatus of claim 7 further comprising logic circuitry to (1) qualify the resetting of a line in the array by an output of the second address decoder, and (2) qualify the reading of a second line in the array by an output of the first address decoder.
12. The apparatus of claim 7 further comprising the sensor array having a plurality of lines of sensor cells connected such that (1) all of the sensor cells in the first line simultaneously receive the reset signal, and (2) all of the sensor cells in the first line simultaneously receive the read signal.
13. A method for controlling a CMOS sensor array containing a first CMOS sensor cell, comprising: receiving a clock signal and generating a first address; generating a reset signal to said first CMOS sensor cell based on said first address; calculating a read delay based on said first address and an offset value; and, generating a read address signal to said first CMOS sensor cell after said read delay.
14. The method of claim 13 , wherein generating a reset signal includes generation of said reset signal to a second CMOS sensor cell based on said first address.
15. The method of claim 13 , wherein generating a read address signal includes generation of said read address signal to a second CMOS sensor cell after said read delay.
16. An apparatus for controlling a CMOS sensor array containing a first CMOS sensor cell, comprising: a first logic circuit for receiving a clock signal and generating a first address; a second logic circuit coupled to said first logic circuit for receiving said first address and generating a reset signal to said first CMOS sensor cell based on said first address; a third logic circuit coupled to said first logic circuit for receiving said first address and calculating a read delay based on said first address and an offset value; and, a fourth logic circuit coupled to said first logic circuit for generating a read address signal to said first CMOS sensor cell after said read delay.
17. The apparatus of claim 16 , wherein first logic circuit comprises an address generator.
18. The apparatus of claim 16 , wherein said second logic circuit comprises a first address decoder.
19. The apparatus of claim 16 , wherein said third logic circuit comprises an adder.
20. The apparatus of claim 16 , wherein said fourth logic circuit comprises a second address decoder.
21. A method for controlling a CMOS sensor array containing a first CMOS sensor cell, comprising: receiving a first clock signal and in response storing a first address; generating a reset signal to said first CMOS sensor cell based on said first address; and then waiting a predetermined number of clock cycles; receiving a second clock signal and in response storing a second address; and, generating a read address signal to said first CMOS sensor cell based on said second address after said predetermined number of clock cycles.
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September 30, 1996
February 15, 2005
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