A DC/DC converter has a semiconductor switch coupled to an inductor, a capacitor and a rectifier. A comparator is coupled to across the rectifier to detect a polarity reversal during the second portion of converter operation to place the converter in a low power mode if the voltage across the rectifier is of an appropriate polarity for reverse current flow. The rectifier may be a synchronous rectifier transistor and the voltage converter placed in a low power mode when the polarity across the synchronous rectifier indicates that reverse current flow is possible. A timing circuit delays the generation of the control signal to place the converter in a low power mode until the steady state current is below a predetermined threshold for a predetermined amount of time. The synchronous rectifier may be turned OFF when the current through the converter falls below another predetermined threshold value and the voltage across the synchronous rectifier will become the voltage across the parasitic diode of the FET synchronous rectifier.
Legal claims defining the scope of protection, as filed with the USPTO.
1. In a voltage converter comprising a semiconductor switch coupled to an inductor, a capacitor and a rectifier, voltage across the capacitor being an output voltage, a control circuit placing the voltage converter in a reduced power mode comprising: a voltage detector circuit coupled across the rectifier detecting polarity of a voltage across the rectifier and generating a control signal to place the voltage converter in a low power mode when the polarity of the voltage across the rectifier is an appropriate polarity for reverse current flow; and a timing circuit coupled to an output of the voltage detector, the timing circuit delaying the generation of the control signal until a predetermined number of clock cycles has elapsed, whereby the voltage converter is placed in a low power mode only when steady state current is below a predetermined threshold.
2. The circuit of claim 1 wherein the rectifier is a synchronous rectifier transistor, the semiconductor switch and the synchronous rectifier being alternatively driven between ON and OFF states by a control circuit.
3. The circuit of claim 2 wherein the synchronous rectifier is an FET transistor having a parasitic diode formed therein, the parasitic diode operating as a free wheeling diode when the synchronous rectifier FET is disabled.
4. The circuit of claim 1 wherein the voltage converter is a buck DC/DC converter.
5. The circuit of claim 1 wherein the voltage converter is a boost converter.
6. The circuit of claim 1 wherein the voltage converter is a buck/boost converter.
7. The circuit of claim 1 wherein the voltage detector circuit comprises a voltage comparator which generates a logic signal when the voltage across the rectifier is of opposite polarity from the voltage across the rectifier during full load operation.
8. A DC/DC converter for generating a voltage at an output which is lower than a voltage supplied to an input comprising: an NMOS transistor coupled between the voltage supply and the series connection of an inductor and a capacitor, voltage across the capacitor being the output voltage; an NMOS synchronous rectifier transistor connected in parallel to the series connected inductor and capacitor, the synchronous rectifier having a parasitic diode coupled in parallel thereto; a control circuit coupled to the NMOS transistor and the NMOS synchronous rectifier transistor and providing a drive signal between substantially the supply voltage and substantially a reference voltage; and a voltage detector circuit coupled across the NMOS synchronous rectifier transistor detecting polarity of a voltage across the NMOS synchronous rectifier transistor and generating a control signal to place the converter in a low power mode when the polarity across the synchronous rectifier indicates that reverse current flow is possible; and a timing circuit coupled to an output of the voltage detector, the timing circuit delaying the generation of the control signal until a predetermined number of clock cycles has elapsed, whereby the voltage converter is placed in a low power mode only when steady state current is below a predetermined threshold.
9. A method for operating a voltage converter having a semiconductor switch coupled to an inductor, a capacitor and a rectifier, comprising: detecting voltage polarity across the rectifier and comparing it to polarity at full load; generating a control signal if the polarity detected is opposite the polarity at full load; placing the converter in a low power mode; and counting a number of clock cycles during which the polarity must remain opposite that of full load current, and generating the control signal only if the polarity remains opposite of full load current for a predetermined number of clock cycles.
10. A voltage converter comprising: a first switching transistor coupled to a first voltage supply, an inductor, and a capacitor, voltage across the capacitor being an output voltage; a rectifier coupled to the inductor to allow a collapse of the magnetic field of the inductor to charge the capacitor; a voltage comparator coupled across the rectifier and detecting a polarity of voltage across the rectifier; a control circuit responsive to an output of the voltage comparator indicative of a polarity reversal across the rectifier during the decay of the inductor magnetic field, to generate a control signal which places the voltage converter in a low power mode; and to a timing circuit coupled to an output of the voltage detector, the timing circuit delaying the generation of the control signal until a predetermined number of clock cycles has elapsed, whereby the voltage converter is placed in a low power mode only when steady state circuit is below a predetermined threshold.
11. The circuit of claim 10 wherein the rectifier is a synchronous rectifier transistor, the semiconductor switch and the synchronous rectifier being alternatively driven between ON and OFF states by a control circuit.
12. The circuit of claim 10 wherein the control circuit includes a low current detector circuit, the control circuit disabling the synchronous rectifier during operation below a predetermined current threshold.
13. The circuit of claim 10 wherein the synchronous rectifier is an FET transistor having a parasitic diode formed therein, the parasitic diode operating as a free wheeling diode when the synchronous rectifier FET is disabled.
14. The circuit of claim 10 wherein the voltage converter is a buck DC/DC converter.
15. The circuit of claim 10 wherein the voltage converter is a boost converter.
16. The circuit of claim 10 wherein the voltage converter is a buck/boost converter.
17. The circuit of claim 10 wherein the voltage detector circuit comprises a voltage comparator which generates a logic signal when the voltage across the rectifier is of opposite polarity from the voltage across the rectifier during full load operation.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 15, 2002
February 22, 2005
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