The corrosion of a pad portion on TEG is prevented, and the wettability of a solder and the shear strength after solder formation of a pad portion of an actual device are improved. A third layer wiring M3 on a chip area CA of a semiconductor wafer and a third layer wiring M3 on a scribe area SA are respectively comprised of a TiN film M3a, an Al alloy film M3b, and a TiN film M3c. A second pad portion PAD2 as the top of a rewiring 49 on the chip area CA is cleaned. Alternatively, an Au film 53a is formed thereon by an electroles splating method. Further, after the formation of the Au film 53a, a retention test is carried out. Thereafter, further, an Au film 53b is formed and a solder bump electrode 55 is formed. As a result, it is possible to prevent the corrosion of a first pad portion PAD1 of the third layer wiring M3 on the scribe area SA which is TEG due to a plating solution or the like by the TiN film M3c. Further, it is possible to improve the wettability of a solder and the shear strength after solder formation of the second pad portion PAD2 by the Au films 53a and 53b.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming a first wiring having a first conductive film and a second conductive film thereon in a chip area of a semiconductor wafer, and forming a pattern for test having the first conductive film and the second conductive film thereon in a scribe area of the semiconductor wafer; (b) forming a second wiring on the first wiring via an insulating film; and (c) cleaning a pad area which is a part of the second wiring with the second conductive film as the surface of the pattern for test being exposed.
2. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the first conductive film contains Al (aluminum) or Cu (copper) as a main component.
3. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the second conductive film is comprised of a single layer film of a TiN (titanium nitride) film, a Ta (tantalum) film, a TaN (tantalum nitride) film, a W (tungsten) film or a WN (tungsten nitride) film, or a multilayer film of these films.
4. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the cleaning is carried out by using an acidic cleaning solution.
5. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , further comprising: subsequent to the step (c), a step (d) of carrying out an evaluation of the pattern for test or a portion electrically connected to the pattem for test by using the pattern for test.
6. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the first wiring is electrically connected to the pattern for test.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 14, 2003
March 1, 2005
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