A main memory and a higher-speed local memory are externally connected to a microprocessor. The entire load module is developed in the main memory. A part or all of the instruction codes in the load module developed in the main memory are stored in the local memory. A memory management unit for data converts a logical address of the entire load module into a physical address of the main memory. A memory management unit for instructions converts a logical address of the instruction code stored in the local memory into a physical address of the local memory. A CPU core gains the instruction code from the local memory at the time of execution of the instruction.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A microprocessor to which a plurality of memory units including a first memory unit and a second memory unit and having physical addresses different from each other are externally connected, said microprocessor comprising: a first address conversion unit which carries out a first address conversion by assigning a first physical address of said first memory unit to a first logical address of a load module stored in said first memory unit, wherein said load module includes an instruction code and numerical data; a copying unit which copies said instruction code from said load module stored in said first memory unit to said second memory unit; and a second address conversion unit which carries out a second address conversion different from the first address conversion by assigning a second physical address of said second memory unit to a second logical address of the instruction code copied to said second memory unit, wherein said first address conversion unit comprises a first comparator that compares a requested logical address with said first logical address, and said second address conversion unit comprises a second comparator that compares said requested logical address with said second logical address.
2. The microprocessor according to claim 1 , wherein when said load module stored in said second memory unit is accessed, said first address conversion unit assigns the physical address of said first memory unit to the logical address of said load module to be accessed, and said second address conversion unit assigns the physical address of said second memory unit to said logical address of the instruction code from said load module to be accessed.
3. The microprocessor according to claim 1 , wherein said load module stored in said first memory unit includes data for image processing and the instruction codes for image processing.
4. A microprocessor to which a plurality of memory units including a first memory unit and a second memory unit and having physical addresses different from each other are externally connected, said microprocessor comprising: a first address conversion unit which carries out a first address conversion by assigning a first physical address of said first memory unit to a first logical address of a load module stored in said first memory unit, wherein said load module includes an instruction code and numerical data; a processing unit which temporarily stores and copies said instruction code from said load module stored in said first memory unit to said second memory unit; and a second address conversion unit which carries out a second address conversion different from the first address conversion by assigning a second physical address of said second memory unit to a second logical address of the instruction code copied to said second memory unit, wherein said first address conversion unit comprises a first comparator that compares a requested logical address with said first logical address, and said second address conversion unit comprises a second comparator that compares said requested logical address with said second logical address.
5. The microprocessor according to claim 4 , wherein when said load module stored in said second memory unit is accessed, said first address conversion unit assigns the physical address of said first memory unit to the logical address of said load module to be accessed, and said second address conversion unit assigns the physical address of said second memory unit to said logical address of the instruction code from said load module to be accessed.
6. The microprocessor according to claim 4 , wherein said load module stored in said first memory unit includes data for image processing and the instruction codes for image processing.
7. A device comprising: a plurality of memory units including a first memory unit and a second memory unit and having physical addresses different from each other; a first address conversion unit which carries out a first address conversion by assigning a first physical address of said first memory unit to a first logical address of a load module stored in said first memory unit, wherein said load module includes an instruction code and numerical data; a copying unit which copies said instruction code from said load module stored in said first memory unit to said second memory unit; and a second address conversion unit which carries out a second address conversion different from the first address conversion by assigning a second physical address of said second memory unit to a second logical address of the instruction code copied to said second memory unit, wherein said first address conversion unit comprises a first comparator that compares a requested logical address with said first logical address, and said second address conversion unit comprises a second comparator that compares said requested logical address with said second logical address.
8. The device according to claim 7 , wherein when said load module stored in said second memory unit is accessed, said first address conversion unit assigns the physical address of said first memory unit to the logical address of said load module to be accessed, and said second address conversion unit assigns the physical address of said second memory unit to said logical address of the instruction code from said load module to be accessed.
9. The device according to claim 7 , wherein said load module stored in said first memory unit includes data for image processing and the instruction codes for image processing.
10. The device according to claim 7 , wherein the access speed of said second memory unit is faster than the access speed of said first memory unit.
11. The device according to claim 10 , wherein said second memory unit comprises a synchronous DRAM.
12. A device comprising: a plurality of memory units including a first memory unit and a second memory unit and having physical addresses different from each other; a first address conversion unit which carries out a first address conversion by assigning a first physical address of said first memory unit to a first logical address of a load module stored in said first memory unit, wherein said load module includes an instruction code and numerical data; a processing unit which temporarily stores and copies said instruction code from said load module stored in said first memory unit to said second memory unit; and a second address conversion unit which carries out a second address conversion different from the first address conversion by assigning a second physical address of said second memory unit to a second logical address of the instruction code copied to said second memory unit, wherein said first address conversion unit comprises a first comparator that compares a requested logical address with said first logical address, and said second address conversion unit comprises a second comparator that compares said requested logical address with said second logical address.
13. The device according to claim 12 , wherein when said load module stored in said first memory unit is accessed, said first address conversion unit assigns the physical address of said first memory unit to the logical address of said load module to be accessed, and said second address conversion unit assigns the physical address of said second memory unit to said logical address of the instruction code from said load module to be accessed.
14. The device according to claim 12 , wherein said load module stored in said first memory unit includes data for image processing and image processing instruction codes.
15. The device according to claim 12 , wherein the access speed of said second memory unit is faster than the access speed of said first memory unit.
16. The device according to claim 15 , wherein said second memory unit comprises a synchronous DRAM.
17. The microprocessor of claim 1 , wherein the operating speed of the second memory unit is faster than the operating speed of the first memory unit.
18. The microprocessor according to claim 1 , wherein the first address conversion unit carries out the first address conversion for information including the numerical data.
19. The microprocessor according to claim 1 , wherein the second address conversion unit carries out the second address conversion for the instruction code.
20. The microprocessor according to claim 4 , wherein the first address conversion unit carries out the first address conversion for information including the numerical data.
21. The microprocessor according to claim 4 , wherein the second address conversion unit carries out the second address conversion for the instruction code.
22. The device according to claim 7 , wherein the first address conversion unit carries out the first address conversion for information including the numerical data.
23. The device according to claim 7 , wherein the second address conversion unit carries out the second address conversion for the instruction code.
24. The device according to claim 12 , wherein the first address conversion unit carries out the first address conversion for information including the numerical data.
25. The device according to claim 12 , wherein the second address conversion unit carries out the second address conversion for the instruction code.
26. A method of accessing a plurality of memory units, including a first memory unit and a second memory unit, the memory units having differing physical addresses, the method comprising: a first address conversion step which carries out a first address conversion by comparing a requested logical address with a first logical address and assigning a first physical address of said first memory unit to a load module logical address for a load module stored in said first memory unit, wherein said load module includes an instruction code and numerical data; a copying step which copies said instruction code from said load module stored in said first memory unit to said second memory unit; and a second address conversion step which carries out a second address conversion different from the first address conversion by comparing said requested logical address with a second logical address and assigning a second physical address of said second memory unit to an instruction code logical address for the instruction code copied to said second memory unit.
27. The method according to claim 26 , wherein when said load module stored in said second memory unit is accessed, the first address conversion step assigns the physical address of said first memory unit to the load module logical address of said load module to be accessed, and the second address conversion step assigns the physical address of said second memory unit to said instruction code logical address of the instruction code from said load module to be accessed.
28. The method according to claim 26 , wherein said load module stored in said first memory unit includes data for image processing and image processing instruction codes.
29. The method according to claim 26 , wherein the first address conversion step carries out the first address conversion for information including the numerical data.
30. The method according to claim 26 , wherein the second address conversion step carries out the second address conversion for the instruction code.
31. A method of accessing a plurality of memory units, the memory units including a first memory unit and a second memory unit, wherein the memory units have differing physical addresses, the method comprising: a first address conversion step which carries out a first address conversion by comparing a requested logical address with a first logical address and assigning a first physical address of said first memory unit to a load module logical address of a load module stored in said first memory unit, wherein said load module includes an instruction code and numerical data; a processing step which temporarily stores and copies said instruction code from said load module stored in said first memory unit to said second memory unit; and a second address conversion step which carries out a second address conversion different from the first address conversion by comparing said requested logical address with a second logical address and assigning a second physical address of said second memory unit to an instruction code logical address of the instruction code copied to said second memory unit.
32. The method according to claim 31 , wherein when said load module stored in said second memory unit is accessed, the first address conversion step assigns the physical address of said first memory unit to the load module logical address of said load module to be accessed, and the second address conversion step assigns the physical address of said second memory unit to said instruction code logical address of the instruction code from said load module to be accessed.
33. The method according to claim 31 , wherein said load module stored in said first memory unit includes data for image processing and image processing instruction codes.
34. The method according to claim 31 , wherein the first address the first address conversion for information including the numerical data.
35. The method according to claim 31 , wherein the second address conversion step carries out the second address conversion for the instruction code.
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August 31, 2000
March 1, 2005
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