Decoder circuit

1. A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential; and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the second decode node to a discharging potential; and second selection circuitry coupled to a respective one of the output lines and operable in response to a second enable signal to select that output line if the second discharge node has not discharged; wherein the first enable signal is derived from the potential of the second decode node.

2. A decode circuit as claimed in claim 1 , wherein the first discharging circuitry comprises a plurality of transistors having their drains connected to the first decode node, their sources connected to the discharging potential and their gates connected to receive a discharging signal dependent on the status of a respective one of the input lines.

3. A decode circuit as claimed in claim 2 , wherein each discharging signal represents an inverted or non-inverted version of the respective one of the input lines.

4. A decode circuit as claimed in claims 1 , 2 , or 3 , wherein the first precharge circuitry comprises a precharge transistor having its source connected to the precharge potential and its drain connected to the decode node.

5. A decode circuit as claimed in claim 1 , wherein the first selection circuitry comprises a selection transistor having its gate connected to the first decode node, its source connected to receive the first enable signal, and its drain arranged to provide a selection signal for the respective one of the output lines.

6. A decode circuit as claimed in claim 5 , further comprising: an inverter responsive to the selection signal to drive the respective one of the output lines.

7. A decode circuit as claimed in claim 6 , wherein the first selection circuitry is operable to select the respective one of the output lines by reducing the potential on the drain of the selection transistor.

8. A decode circuit as claimed in claims 5 , 6 , or 7 , further comprising: precharge circuitry for precharging the drain of the selection transistor to a charging potential.

9. A decode circuit as claimed in claim 4 , wherein the further precharge circuitry comprises a further precharge transistor having its source connected to the precharge potential and its drain connected to the drain of the selection transistor.

10. A decode circuit as claimed in claim 9 , wherein the precharge transistor and the further precharge transistor are operable in response to a common precharge signal.

11. A decode circuit as claimed in claims 5 , 6 , or 7 , wherein the second decode node is connected to the source of the selection transistor.

12. A decode circuit as claimed in claim 11 , further comprising a first holding transistor having its source connected to a charging potential, its drain connected to the decode node and its gate connected to the drain of the selection transistor.

13. A decode circuit as claimed in claim 12 , comprising a second holding transistor having its drain connected to a charging potential, its drain connected the drain of the selection transistor and its gate connected to the decode node.

14. A decode circuit as claimed in claim 13 , wherein the second enable signal is derived from the potential of the first decode node.

15. A decode circuit as claimed in claim 14 , wherein the first selection circuitry is capable of selecting its respective output line in response to Opposite values of the input lines than those in response to which the second selection circuitry is capable of selecting its respective output line.

16. A decode circuit as claimed in claim 15 , wherein each output line is a wordline of a memory unit.

17. A decode circuit as claimed in claim 16 , wherein the input lines represent an address for selection.