A data structure is disclosed. Such a data structure includes a thread control block and a message. The thread control block is described by a first data structure and the message is described by a second data structure. Additionally, the first data structure includes the second data structure. Thus, a data structure according to the present invention combines a thread control block structure and a message structure to provide the various benefits described herein. The first data structure may be configured, for example, to store information used to control execution of a thread, with the second data structure configured to store a message.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A data structure comprising a combined thread control block/message structure, said combined thread control block/message structure comprising: a thread control block structure configured to store information used to control execution of a thread, said thread control block structure further comprising: a message structure configured to store a message; a process control block pointer that points to a process control block; processor information; and stack information.
2. The data structure of claim 1 , wherein said process control block comprises: memory information; thread information; device driver information; and stack information.
3. The data structure of claim 1 , wherein said processor information comprises: a processor identifier; and thread information.
4. The data structure of claim 1 , wherein said message structure further comprises: control information.
5. The data structure of claim 4 , wherein said message structure further comprises: data.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 28, 2000
March 8, 2005
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