A silicon on insulator (SOI) CMOS circuit, macro and integrated circuit (IC) chip. The chip or macro may include be an SRAM in partially depleted (PD) SOI CMOS. Most field effect transistors (FETs) do not have body contacts. FETs otherwise exhibiting a sensitivity to history effects have body contacts. The body contact for each such FET is connected to at least one other body contact. A back bias voltage may be provided to selected FETs.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit (IC) chip comprising: a plurality of devices connected together into a circuit; at least two of said plurality of devices being coupled body devices, each coupled body device having body contact connected to another body contact on another said coupled body device, wherein charge induced in each said coupled body device is shared with connected said coupled body devices, history effects being substantially reduced in said coupled body devices; and at least one other of said plurality of devices is a floating body devices.
2. An IC as in claim 1 , wherein said plurality of devices are field effect transistors (FETs).
3. An IC as in claim 2 , further comprising a back bias voltage connected to said body contact at ones of said coupled body FETs.
4. An IC as in claim 3 , wherein said back bias voltage is ground.
5. An IC as in claim 2 , wherein said IC is a CMOS IC, said CMOS IC further including an array of static random access memory (SRAM) cells.
6. An IC as in claim 5 , wherein said IC is on a partially depleted (PD) silicon on insulator (SOI) chip.
7. An IC as in claim 6 , wherein said at least two coupled body devices includes a pair of cross coupled FETs.
8. An IC as in claim 7 , wherein said cross coupled FETs are NFETs in a sense amplifier.
9. An IC as in claim 2 , wherein said at least two includes at least one pair of coupled floating body FETs, charge induced in each of said at least one pair being shared with the other of said at least one pair.
10. A CMOS silicon on insulator (SOI) static random access memory (SRAM), a plurality of FETs connected together forming said CMOS SOI SRAM, a majority of said FETs being floating body FETs, said CMOS SOI SRAM comprising: an array of SRAM cells; a bit decoder selecting an array column; a word decoder selecting an array row; a plurality of sense amplifiers sensing data at selected ones of said array cells; a data input/output (I/O) driver selectively passing sensed data external to said SRAM and forwarding received data input to said selected ones; and a plurality of coupled body FETs, each of said coupled body FETs including a body contact connected to a body contact at another coupled body FET, wherein charge induced in each said coupled body FET is shared with connected said coupled body FETs, history effects being substantially reduced in said coupled body FETs.
11. A CMOS SOI SRAM as in claim 10 , said bit decoder comprising: a plurality of column select drivers, a selected one of said column drivers selecting said array column, each of said column select drivers comprising a pair of coupled body FETs, a back bias voltage being provided to each of said pair at said body.
12. A CMOS SOI SRAM as in claim 11 , wherein said back bias voltage is ground.
13. A CMOS SOI SRAM as in claim 11 , wherein said pair of coupled body FETs are connected between a complementary bit line pair and a complementary data in pair, each of said column select drivers further comprising: a column restore selectively restoring said complementary bit line pair to an unselected voltage and equalizing voltage differences between said complementary bit line pair; a pair of read NFETs selectively coupling said complementary bit line pair to a data line pair; and a write control circuit, said pair of coupled body FETs selectively coupling said complementary bit line pair to said complementary data in pair responsive to said write control circuit.
14. A CMOS SOI SRAM as in claim 13 , wherein said column restore comprises: a first inverter receiving a bit select signal, said first inverter driving the gates of said pair of read NFETs; a second inverter receiving the output of said first inverter; a pair of restore FETs connected between a supply voltage and said complementary bit line pair, said second inverter driving gates of said pair of restore FETs; and an equalization FET connected between said complementary bit line pair, said first inverter driving the gate of said equalization FET.
15. A CMOS SOI SRAM as in claim 14 , wherein said write control circuit is a NOR gate receiving said output of said first inverter and a write control signal.
16. A CMOS SOI SRAM as in claim 13 , wherein said pair of read NFETs and FETs in each of said column restore and said write control circuit are ones of said floating body FETs.
17. A CMOS SOI SRAM as in claim 10 , each of said sense amplifiers comprising: a pair of cross coupled NFETs, said cross coupled NFETs being a pair of said coupled body FETs, said body contact of a first of said pair being connected to a body contact of a second of said pair.
18. A CMOS SOI SRAM as in claim 17 , wherein said cross coupled NFETs are connected between a complementary pair of data lines and a sense enable node, each of said sense amplifiers further comprising: a data line restore selectively restoring said pair of data lines to an unselected voltage and equalizing voltage differences between said pair; a pair of cross coupled PFETs connected between said pair of data lines and a supply voltage; a sense enable receiving a sense enable signal and driving said sense enable node; and a driver receiving sensed data from said pair of data lines and redriving said sensed data.
19. A CMOS SOI SRAM as in claim 18 , wherein said data restore comprises: a first inverter receiving a restore signal; a second inverter receiving the output of said first inverter; a pair of restore FETs between a supply voltage and said pair of data lines; and an equalization FET connected between said pair of data lines, said second inverter further driving the gate of said pair of restore FETs and said equalization FET.
20. A CMOS SOI SRAM as in claim 18 , wherein said sense enable comprises a pair of series connected inverters.
21. A CMOS SOI SRAM as in claim 18 , wherein said driver comprises: an inverter, one of said pair of data lines driving said inverter; and a tristatable driver driven by said first inverter and another of said pair of data lines, said tristatable driver redriving sensed data.
22. A CMOS SOI SRAM as in claim 18 , wherein said pair of cross coupled PFETs and FETs in each of said data restore, said sense enable and said driver ones of said floating body FETs.
23. A CMOS SOI SRAM as in claim 10 , wherein said CMOS SOI SRAM is on a partially depleted (PD) SOI chip.
24. A partially depleted (PD) CMOS silicon on insulator (SOI) chip, a plurality of FETs connected together forming a circuit on said PD CMOS SOI chip, a majority of said FETs being floating body FETs, said circuit including a static random access memory (SRAM), said SRAM comprising: an array of SRAM cells; a bit decoder including a plurality of column select drivers each selecting an array column, each of said column select drivers comprising: a pair of coupled body FETs, each including a body contact and connected to another coupled body FET, wherein charge induced in each said coupled body FET is shared with connected said coupled body FETs, history effects being substantially reduced in said coupled body FETs, and a back bias voltage being provided to each of said pair at said body; a word decoder selecting an array row; a plurality of sense amplifiers sensing data at selected ones of said array cells, each of said sense amplifiers comprising a pair of cross coupled NFETs connected between a complementary pair of data lines and a sense enable node, said cross coupled NFETs being a pair of said coupled body FETs, said body contact of a first of said pair being connected to a body contact of a second of said pair, charge induced into the body of either of said pair being shared by said pair; and a data input/output (I/O) driver selectively passing sensed data external to said SRAM and forwarding received data input to said selected ones.
25. A PD CMOS SOI chip as in claim 24 , wherein said back bias voltage is ground.
26. A PD CMOS SOI chip as in claim 24 , wherein said pair of coupled body FETs in said bit decoder are connected between a complementary bit line pair and a complementary data in pair, each of said column select drivers further comprising: a column restore selectively restoring said complementary bit line pair to an unselected voltage and equalizing voltage differences between said complementary bit line pair; a pair of read NFETs selectively coupling said complementary bit line pair to a complementary data line pair; and a NOR gate receiving an output of said column restore and a write control signal, an output of said NOR gate driving the gates of said pair of coupled body FETs, driven said coupled body FETs coupling said complementary bit line pair to said complementary data in pair.
27. A PD CMOS SOI chip as in claim 26 , wherein said column restore comprises: a first inverter receiving a bit select signal, said first inverter providing said output received by said NOR gate and driving the gates of said pair of read NFETs; a second inverter receiving the output of said first inverter; a pair of restore FETs between a supply voltage and said complementary bit line pair, said second inverter driving gates of said pair of restore FETs; and an equalization FET connected between said complementary bit line pair, said first inverter driving the gate of said equalization FET.
28. A PD CMOS SOI chip as in claim 27 , each of said sense amplifiers further comprising: a data line restore selectively restoring said pair of data lines to an unselected voltage and equalizing voltage differences between said pair of data lines; a pair of cross coupled PFETs connected between said pair of data lines and a supply voltage; a sense enable receiving a sense enable signal and driving said sense enable node; and a driver receiving sensed data from said pair of data lines and redriving said sensed data.
29. A PD CMOS SOI chip as in claim 28 , wherein said data restore comprises: a first inverter receiving a restore signal; a second inverter receiving the output of said first inverter; a pair of restore FETs between a supply voltage and said complementary pair of data lines; and an equalization FET connected between said pair of data lines, said second inverter further driving gates of said pair of restore FETs and the gate of said equalization FET.
30. A PD CMOS SOI chip as in claim 29 , wherein said sense enable comprises a pair of series connected inverters.
31. A PD CMOS SOI chip as in claim 28 , wherein said driver comprises: an inverter, one of said pair of data lines driving said inverter; and a tristatable driver driven by said first inverter and another of said pair of data lines, said tristatable driver redriving said sensed data.
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May 12, 2003
March 15, 2005
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