The present invention is generally directed to a fully-depleted SOI device structure. In one illustrative embodiment, the device comprises first, second and third doped regions formed in the bulk substrate, wherein the dopant concentration level in the doped regions is greater than the dopant concentration in the bulk substrate. The first doped region is substantially aligned with the gate electrode of the device, while the second and third doped regions are vertically spaced apart from the first doped region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A device, comprising: a transistor formed above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer, said transistor being comprised of a gate electrode, said bulk substrate being doped with a dopant material at a first concentration level; and first, second and third doped regions formed in said bulk substrate, said first, second and third doped regions being comprised of a dopant material that is the same type as said bulk substrate dopant material, said first, second and third doped regions having a greater concentration level of dopant material than said first concentration level, said first doped region being substantially aligned with said gate electrode and vertically spaced apart from said second and third doped regions.
2. The device of claim 1 , wherein said transistor is comprised of at least one of an NMOS and PMOS device.
3. The device of claim 1 , wherein said buried oxide layer is comprised of silicon dioxide and has a thickness ranging from approximately 5-50 nm.
4. The device of claim 1 , wherein said active layer is comprised of silicon and has a thickness of approximately 5-30 nm.
5. The device of claim 1 , wherein said gate electrode is comprised of polysilicon and has a thickness of approximately 100-150 nm.
6. The device of claim 1 , wherein said gate electrode has a thickness and wherein said first doped region is vertically spaced apart from said second and third doped regions by a distance that corresponds approximately to said thickness of said gate electrode.
7. The device of claim 1 , wherein said bulk substrate is doped with a P-type dopant material at a concentration level of approximately 10 15 ions/cm 3 and said first, second and third doped regions are doped with a P-type dopant material at a dopant concentration level of at least approximately 10 16 ions/cm 3 .
8. The device of claim 1 , wherein said bulk substrate is doped with an N-type dopant material at a concentration level of approximately 10 15 ions/cm 3 and said first, second and third doped regions are doped with an N-type dopant material at a dopant concentration level of at least approximately 10 16 ions/cm 3 .
9. The device of claim 1 , wherein said first, second and third doped regions each have a thickness of approximately 10-50 nm.
10. The device of claim 1 , wherein each of said second and third doped regions has an inner edge that is approximately aligned with respect to said gate electrode.
11. The device of claim 1 , wherein said first doped region has an upper surface that is positioned approximately 0-5 nm below an interface between said buried oxide layer and said bulk substrate.
12. The device of claim 1 , wherein said second and third doped regions each have an upper surface that is positioned below an interface between the buried oxide layer and the bulk substrate by a distance that corresponds approximately to a thickness of the gate electrode.
13. The device of claim 1 , further comprising a source region, a drain region, a sidewall spacer and a plurality of conductive interconnections.
14. A device, comprising: a transistor formed above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer, said transistor being comprised of a gate electrode having a thickness, said bulk substrate being doped with a dopant material at a first concentration level; and first, second and third doped regions formed in said bulk substrate, said first, second and third doped regions being comprised of a dopant material that is the same type as said bulk substrate dopant material, said first, second and third doped regions having a greater concentration level of dopant material than said first concentration level and at least a concentration level of approximately 10 16 ions/cm 3 , said first doped region being substantially aligned with said gate electrode and vertically spaced apart from said second and third doped regions by a distance that corresponds approximately to said thickness of said gate electrode.
15. The device of claim 14 , wherein said transistor is comprised of at least one of an NMOS and PMOS device.
16. The device of claim 14 , wherein said buried oxide layer is comprised of silicon dioxide and has a thickness ranging from approximately 5-50 nm.
17. The device of claim 14 , wherein said active layer is comprised of silicon and has a thickness of approximately 5-30 nm.
18. The device of claim 14 , wherein said gate electrode is comprised of polysilicon and has a thickness of approximately 100-150 nm.
19. The device of claim 14 , wherein said bulk substrate is doped with a P-type dopant material at a concentration level of approximately 10 15 ions/cm 3 and said first, second and third doped regions are doped with a P-type dopant material at a dopant concentration level of at least approximately 10 16 ions/cm 3 .
20. The device of claim 14 , wherein said bulk substrate is doped with an N-type dopant material at a concentration level of approximately 10 15 ions/cm 3 and said first, second and third doped regions are doped with an N-type dopant material at a dopant concentration level of at least approximately 10 16 ions/cm 3 .
21. The device of claim 14 , wherein said first, second and third doped regions each have a thickness of approximately 10-50 nm.
22. The device of claim 14 , wherein each of said second and third doped regions has an inner edge that is approximately aligned with respect to said gate electrode.
23. The device of claim 14 , wherein said first doped region has an upper surface that is positioned approximately 0-5 nm below an interface between said buried oxide layer and said bulk substrate.
24. The device of claim 14 , wherein said second and third doped regions each have an upper surface that is positioned below an interface between the buried oxide layer and the bulk substrate by a distance that corresponds approximately to the thickness of the gate electrode.
25. The device of claim 14 , further comprising a source region, a drain region, a sidewall spacer and a plurality of conductive interconnections.
26. A device, comprising: a transistor formed above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer comprised of silicon, said transistor being comprised of a gate electrode having a thickness, said bulk substrate being doped with a dopant material at a first concentration level, said buried oxide layer being comprised of silicon dioxide; and first, second and third doped regions formed in said bulk substrate, said first, second and third doped regions being comprised of a dopant material that is the same type as said bulk substrate dopant material, said first, second and third doped regions having a thickness of approximately 10-50 nm and a greater concentration level of dopant material than said first concentration level and at least a concentration level of at least approximately 10 16 ion/cm 3 , said first doped region being substantially aligned with said gate electrode and vertically spaced apart from said second and third doped regions by a distance that corresponds approximately to said thickness of said gate electrode.
27. The device of claim 26 , wherein said transistor is comprised of at least one of an NMOS and PMOS device.
28. The device of claim 26 , wherein said buried oxide layer has a thickness ranging from approximately 5-50 nm.
29. The device of claim 26 , wherein said active layer has a thickness of approximately 5-30 nm.
30. The device of claim 26 , wherein said gate electrode is comprised of polysilicon and has a thickness of approximately 100-150 nm.
31. The device of claim 26 , wherein said bulk substrate is doped with a P-type dopant material at a concentration level of approximately 10 15 ions/cm 3 and said first, second and third doped regions are doped with a P-type dopant material at a dopant concentration level of at least approximately 10 16 ions/cm 3 .
32. The device of claim 26 , wherein said bulk substrate is doped with an N-type dopant material at a concentration level of approximately 10 15 ions/cm 3 and said first, second and third doped regions are doped with an N-type dopant material at a dopant concentration level of at least approximately 10 16 ions/cm 3 .
33. The device of claim 26 , wherein each of said second and third doped regions has an inner edge that is approximately aligned with respect to said gate electrode.
34. The device of claim 26 , wherein said first doped region has an upper surface that is positioned approximately 0-5 nm below an interface between said buried oxide layer and said bulk substrate.
35. The device of claim 26 , wherein said second and third doped regions each have an upper surface that is positioned below an interface between the buried oxide layer and the bulk substrate by a distance that corresponds approximately to the thickness of the gate electrode.
36. The device of claim 26 , further comprising a source region, a drain region, a sidewall spacer and a plurality of conductive interconnections.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 9, 2004
April 5, 2005
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