A voltage-mode boosting write driver circuit (40) having a pair of voltage boosting PMOS transistor sets (44, 46) coupled to a high current H-switch (42). One set (44) of the boosting PMOS transistors correspondingly pulls output pin HY high, while the other transistor set (46) correspondingly pulls output pin HX high and the other output pin HY low thereby significantly improving the head voltage swing, and also achieving a faster slew rate. Moreover, resistors (R3, R4) of the H-switch are both matched to each other and impedance matched to a flex cable (T0) interconnection impedance, which interconnection is coupled to the thin film head, to thereby eliminate signal reflection such that the write current (Iw) settles quickly with minimum ringing to achieve a high data rate. Moreover, less power dissipation and smaller number of devices used are achieved by making use of existing transient currents of the pre-driver emitter follower stage.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A write driver circuit having a differential signal input, comprising: a write head; an H-switch having a first and second transistor with a first node defined therebetween, and a third and fourth transistor with a second node defined therebetween, wherein said first and second nodes are adapted to drive the write head; a first boosting transistor set coupled to said differential signal input adapted to pull said first node low and said second node high; a second boosting transistor set coupled to said differential signal input adapted to pull said first node high and said second node low; and a pre-driver including a fifth transistor coupled between said differential signal input and said H-switch first transistor, and a sixth transistor coupled between said differential signal input and said H-switch third transistor, wherein said fifth and sixth transistors transient currents during switching, wherein said transient currents drive said first and second boosting transistor set.
2. The write driver circuit specified in claim 1 wherein said first boosting transistor set includes at least one PMOS transistor.
3. The write driver circuit specified in claim 2 wherein said first boosting transistor set includes a first and second PMOS transistor.
4. The write driver circuit specified in claim 3 wherein said second boosting set includes a pair of PMOS transistors.
5. The write driver circuit specified in claim 1 further comprising a first resistor coupled between said first node and said second transistor, and a second resistor coupled between said second node and said fourth transistor, wherein the sum of said first and second resistor resistance is matched to an impedance of the write head.
6. The write driver circuit specified in claim 5 wherein said first and second resistors are matched.
7. The write driver circuit specified in claim 1 wherein said first and second boosting transistor sets are adapted to create both a larger voltage swing and a faster slew rate at said first and second node from that produced by the circuit without said first and second boosting transistor sets.
8. A write driver circuit having a differential signal input, comprising: a write head; an H-switch having a first and second transistor with a first node defined therebetween, and a third and fourth transistor with a second node defined therebetween, wherein said first and second nodes are adapted to drive the write head; a first boosting transistor set coupled to said differential signal input adapted to pull said first node low and said second node high; and a second boosting transistor set coupled to said differential signal input adapted to pull said first node high and said second node low, wherein said first boosting transistor set includes a first and second PMOS transistor; and wherein said first and second PMOS transistors are coupled in parallel.
9. The write driver circuit specified in claim 8 wherein said first PMOS transistor is coupled to said second node, and said second PMOS transistor is coupled to the H-switch first transistor.
10. The write driver circuit specified in claim 9 wherein the H-switch is disposed between an upper and lower voltage rail, the first transistor has a base, and wherein said second PMOS transistor is adapted to pull said first transistor base toward said upper voltage rail and said first node toward said lower voltage rail.
11. The write driver circuit specified in claim 10 wherein said first PMOS transistor is adapted to pull said second node toward said upper voltage rail.
12. A method of increasing a slew rate and voltage swing at a first and second output of an H-switch adapted to drive a write head, comprising the step of: utilizing a set of boosting transistors coupled to the H-switch to increase a pull-up voltage at the first output while simultaneously increasing a pull-down voltage at the second output; and using a pre-driver to drive said H-switch, wherein transient currents of said pre-driver drive said boosting transistors.
13. The method as specified in claim 12 wherein the boosting transistors comprise a pair of PMOS transistors.
14. The method as specified in claim 13 wherein a first of the boosting transistors is coupled to one half of the H-switch, and a second boosting transistor is coupled to the other half of the H-switch.
15. The method as specified in claim 14 wherein the first boosting transistor pulls the second output up while the second boosting transistor drives the respective half of the H-switch harder to responsively pull down the first output.
16. The method as specified in claim 12 further comprising the step of matching the output impedance of the H-switch to an impedance of the write head driven by the first and second output.
17. A write driver circuit having a differential signal input, comprising: an H-switch having a first and second transistor with a first node defined therebetween, and a third and fourth transistor with a second node defined therebetween, wherein said first and second nodes are adapted to drive a write head; a first boosting transistor coupled to said differential input adapted to pull said first node low and said second node high; and a second boosting transistor coupled to said differential input adapted to pull said first node high and said second node low, wherein the H-switch is disposed between an upper and lower voltage rail, the first transistor has a base, and wherein said second boosting transistor is adapted to pull said first transistor base toward said upper voltage rail and said first node toward said lower voltage rail.
18. The write driver circuit specified in claim 17 wherein said first boosting transistor is adapted to pull said second node toward said upper voltage rail.
19. A write driver circuit having a differential signal input, comprising: an H-switch having a first and second transistor with a first node defined therebetween, and a third and fourth transistor with a second node defined therebetween, wherein said first and second nodes are adapted to drive a write head; a first boosting transistor coupled to said differential input adapted to pull said first node low and said second node high; a second boosting transistor coupled to said differential input adapted to pull said first node high and said second node low, and a pre-driver coupled to said H-switch, wherein said pre-driver has transient currents driving said first and second boosting transistors.
20. The write driver circuit specified in claim 19 wherein said first and second boosting transistors comprise PMOS devices.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 19, 2001
April 12, 2005
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