A signal line of a data bus includes first wires on a first board and a second wire on a second board. The second board is installed on the first board to connect the first and second wires with each other in series to establish the signal line. Semiconductor devices are connected with the second wire. In such data bus system, impedance of the second wire is decided according to additional capacitance of the semiconductor device on the second board in order to harmonize impedance of the first board with impedance of the second board.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A data bus system comprising: a first wire laid on a first board as a part of a signal line of a data bus; a second wire laid on a second board which is installed on the first board as a part of the signal line; and a semiconductor device embedded on the second board and connected with the second wire, wherein impedance of the second wire is larger than impedance of the first board, and wherein the second wire comprises a section at least one of whose width, thickness and length is decided according to the additional capacitance of the semiconductor device and the second board comprises at least one inner layer and at least one part of the section is laid on the inner layer.
2. The data bus system claimed in claim 1 , wherein the first wire and second wire are connected with each other in a stubless wiring structure.
3. The data bus system claimed in claim 1 , wherein the whole of the second wire corresponds to the section.
4. The data bus system claimed in claim 1 , wherein: at least two semiconductor devices are embedded on the second board; and the section is prepared for the whole of the semiconductor devices.
5. The data bus system claimed in claim 1 , wherein: at least two semiconductor devices are embedded on the second board; the second wire comprises the same number of the sections as the semiconductor devices; and each of the sections is prepared for one of the semiconductor devices.
6. A memory module board, on which at least one memory chip is embedded, for use in being plugged into a connector on a predetermined motherboard to establish a data bus to the memory chip, wherein an impedance of a wire on the memory module board is larger than an impedance of the motherboards, wherein the wire on the memory module board comprises at least one section, at least one of said section's width, thickness and length is decided according to additional capacitance of the memory chips, and the memory module board further comprises at least one inner layer and at least one part of the section is laid on the inner layer.
7. The memory module board claimed in claim 6 , wherein the memory module board and the motherboard are connected with each other in a stubless wiring structure.
8. The memory module board claimed in claim 6 , wherein the wire on the memory module board corresponds to the section.
9. The memory module board claimed in claim 6 , wherein: at least two semiconductor devices are embedded on the second board; and the section is prepared for the whole of the semiconductor devices.
10. The memory module board claimed in claim 6 , wherein: at least two semiconductor devices are embedded on the second board; the wire on the memory module board comprises the same number of the sections as the semiconductor devices; and each of the sections is prepared for one of the semiconductor devices.
11. A method of wiring a signal line of a data bus, comprising the steps of: laying first wires laid on a first board and second wires laid on at least one second board; installing the second board on the first board to connect the first and second wires with each other in series to establish a signal line; connecting at least one semiconductor device to the second wire; wiring a wire whose impedance is decided according to additional capacitance of the semiconductor device on the second board as the second wire in order to harmonize an impedance of the first board with an impedance of the second board; deciding according to the additional capacitance, a width, thickness and length of at least one section of the second wire; and laying on an inner layer of said second board at least one part of the section.
12. The method claimed in claim 11 , wherein an impedance of the second wire is larger than the impedance of the first board.
13. The method claimed in claim 11 , further comprising the step of connecting the first and second wires to each other in a stubless wiring structure.
14. The method claimed in claim 11 , wherein the whole of the second wire corresponds to the section.
15. The method claimed in claim 14 , further comprising the steps of: embedding at least two semiconductor devices on the second board; and preparing the section all of the semiconductor devices.
16. The method claimed in claim 14 , further comprising the steps of: embedding at least two semiconductor devices on the second board; wherein the second wire comprises the same number of the sections as the semiconductor devices; and wherein each of the sections is prepared for one of the semiconductor devices.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 26, 2002
April 19, 2005
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.