A method of sensing a ferroelectric non-volatile information storage unit comprising two ferroelectric storage capacitors in mutually opposite polarization states, and a sensing circuit for actuating the method. The method comprises the steps of: making a voltage applied across the two storage capacitors substantially zero; starting from this condition, progressively increasing the voltage applied thereacross by supplying a prescribed current, until a first one of the two storage capacitors approaches a condition of polarization state reversal, thereby the voltage applied across said first storage capacitor starts to decrease with respect to the voltage applied across the second storage capacitor; and amplifying a voltage difference between the voltages applied across the two storage capacitors by making the voltage applied across the first storage capacitor substantially zero and the voltage applied across the second storage capacitor substantially equal to a non-zero voltage corresponding to a logic state opposite to a logic state corresponding to the zero voltage.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of sensing a ferroelectric non-volatile information storage unit comprising two ferroelectric storage capacitors in mutually opposite polarization states, the method comprising the steps of: making a voltage applied across the two storage capacitors substantially zero; starting from the condition of substantially zero voltage applied across the two storage capacitors, progressively increasing the voltage applied thereacross by supplying a prescribed current, until a first one of the two storage capacitors approaches a condition of polarization state reversal, thereby the voltage applied across said first storage capacitor starts to decrease with respect to the voltage applied across the second storage capacitor; and amplifying a voltage difference between the voltages applied across the two storage capacitors by making the voltage applied across the first storage capacitor substantially zero and the voltage applied across the second storage capacitor substantially equal to a non-zero voltage corresponding to a logic state opposite to a logic state corresponding to the zero voltage.
2. The method according to claim 1 , comprising the steps of: pre-charging to a first voltage a first and a second circuit nodes, each of which connected to a first plate of a respective storage capacitor, keeping second plates of the two storage capacitors to the first voltage; while keeping the second plates of the two storage capacitors to the first voltage, charging the first and second circuit nodes by supplying the prescribed current, thereby applying to the two storage capacitors an electric field, whereby the first circuit node, connected to the first plate of the storage capacitor polarized as the applied electric field, moves towards a second voltage while the second circuit node, connected to the first plate of the storage capacitor having opposite polarization with respect to the applied electric field, starts to move back towards the first voltage when the voltage of the second circuit node reaches a prescribed value characteristic of the ferroelectric material; amplifying a voltage difference between the first and second circuit nodes by bringing the circuit node associated with storage capacitor polarized as the applied electric field to the second voltage and the other circuit node to the first voltage.
3. The method according to claim 2 , comprising, after the step of amplifying the voltage difference between the first and second circuit nodes, a step of applying a third voltage to the second plates of the storage capacitors for restoring an initial polarization state in the two storage capacitors.
4. A circuit for sensing a ferroelectric non-volatile information storage unit comprising two storage capacitors in mutually opposite polarization states, the circuit comprising: a pre-charge circuit activatable for pre-charging to a first voltage a first and a second circuit nodes each one connected to a first plate of a respective storage capacitor; a plate line for selectively supplying to a second plate of the storage capacitors a plate line voltage equal to the first voltage or to a second voltage, and an amplifying circuit for amplifying a voltage difference between the first and second circuit nodes, bringing one of the first and second circuit nodes to the first voltage and the other circuit node to a third voltage, according to a polarization state of the storage capacitors, characterized in that a current supply is provided for supplying the first and second circuit nodes with a prescribed current, thereby charging the first and second circuit nodes, and in that the plate line supplies to the second plates of the storage capacitors the first voltage while the pre-charge circuit is activated and during the charging of the first and second circuit nodes, the plate line supplying to the second plates of the storage capacitors the second voltage only after the amplifying circuit has amplified the voltage difference between the first and second circuit nodes.
5. The circuit according to claim 4 , in which the current supply supplies the prescribed current to the first and second circuit nodes through the amplifying circuit.
6. The circuit according to claim 5 , in which the current supply comprises a current mirror with a first branch run through by a reference current and at least one second branch run through by a mirrored current, the at least one second branch supplying the mirrored current to the amplifying circuit.
7. The circuit according to claim 6 , in which the amplifying is a circuit comprising a pair of latch-connected inverters having a low-side supply node and a high-side supply node, the high-side supply node being connected to the second branch of the current mirror for receiving the mirrored current.
8. The circuit according to claim 7 , in which the low-side supply node is connected to the first voltage through a switch selectively activatable for supplying to the low-side supply node to the first voltage.
9. A read circuit for reading data from a storage unit that includes two ferroelectric cells each having a respective polarization, the read circuit comprising: an amplifier operable to increase a respective voltage across each of the cells until the polarization of one of the cells partially reverses, and to amplify a difference between the respective voltages caused by the partial reversal.
10. The read circuit of claim 9 wherein the amplifier comprises a sense amplifier.
11. The read circuit of claim 9 , further comprising: a current circuit operable to provide a current to the amplifier; and wherein the amplifier is operable to increase the respective voltage across each of the cells by charging the cells with first and second portions of the current, respectively.
12. The read circuit of claim 9 , further comprising an enable circuit operable to enable the amplifier to amplify the difference between the respective voltages after the polarization of the one cell partially reverses.
13. The read circuit of claim 9 , further comprising a precharge circuit operable to initialize the respective voltages across the cells to a predetermined voltage level before the amplifier begins to increase the respective voltages.
14. The read circuit of claim 9 , further comprising a restore circuit operable to restore the one of the cells to an initial polarization.
15. The read circuit of claim 9 wherein the value of the data corresponds to the polarity of the difference between the voltages across the cells.
16. A memory, comprising: first and second bit lines; a storage unit operable to store data and including first and second ferroelectric storage cells respectively coupled to the first and second bit lines; and a read circuit coupled to the bit lines, operable to increase a respective voltage on each of the first and second bit lines until the respective voltages diverge, and operable to amplify the difference between the divergent voltages.
17. The memory of claim 16 wherein the read circuit comprises a sense amplifier that is operable to amplifier the difference between the divergent voltages.
18. The memory of claim 16 wherein the read circuit comprises a charger that is operable to increase the respective voltage on each of the first and second bit lines by charging the first and second cells with respective first and second currents.
19. The memory of claim 16 wherein the read circuit comprises a charger that is operable to increase the respective voltage on each of the first and second bit lines by charging the first and second cells with respective first and second currents, the first current being substantially equal to the second current.
20. The memory of claim 16 wherein: the first and second bit lines have first and second parasitic capacitances associated therewith; and the read circuit comprises a charger that is operable to increase the respective voltage on each of the first and second bit lines by charging the first and second cells and the first and second parasitic capacitances with respective first and second currents.
21. The memory of claim 16 wherein the read circuit is operable to amplify the difference between the respective voltages a predetermined time after beginning to increase the respective voltages on the first and second bit lines.
22. The memory of claim 16 wherein the read circuit is operable to amplify the difference between the respective voltages after the voltages diverge.
23. The memory of claim 16 wherein the read circuit comprises a precharger that is operable to initialize the first and second bit lines to a predetermined voltage level before the respective voltages on the bit lines begin to increase.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 24, 2002
April 26, 2005
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