Methods and apparatus for forming word line stacks comprise forming a thin nitride layer coupled between a bottom silicon layer and a conductor layer. In a further embodiment, a diffusion barrier layer is coupled between the thin nitride layer and the bottom silicon layer. The thin nitride layer is formed by annealing a silicon oxide film in a nitrogen-containing ambient.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for forming a semiconductor transistor structure, comprising: forming a semiconductor substrate; coupling a gate oxide layer to the semiconductor substrate; coupling a bottom silicon layer to the gate oxide layer; positioning a conductor layer adjacent to the bottom silicon layer; interposing a thin, nitride layer having a low nitrogen concentration of approximately 10 13 ions/cm 3 between the bottom silicon layer and the conductor layer, wherein interposing the nitride layer includes interposing the nitride layer having a thickness of a few atomic layers so as not to inhibit subsequent silicidation.
2. The method of claim 1 , wherein interposing the nitride layer includes interposing the nitride layer having a thickness of approximately less than 20 to 50 angstroms.
3. The method of claim 1 , wherein interposing the nitride layer includes interposing the nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms.
4. The method of claim 1 , wherein interposing the nitride layer includes interposing the nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms.
5. A method for forming a semiconductor memory device, comprising: forming a plurality of memory cells; coupling a plurality of access transistors to the plurality of memory cells; and coupling at least one word line formed over a gate oxide layer to the plurality of access transistors by a method comprising: forming a bottom silicon layer over the gate oxide layer; forming a nitrogen-doped silicon oxide layer over the bottom silicon layer; forming a refractory metal layer on the nitrogen-doped silicon oxide layer; and annealing the refractory metal layer to form a refractory metal silicide conductor layer and a thin, nitride layer having a low nitrogen concentration of approximately 10 13 ions/cm 3 interposed between the bottom silicon layer and the refractory metal silicide conductor layer, wherein annealing the refractory metal layer to form the nitride layer includes annealing the refractory metal layer to form the nitride layer having a thickness of a few atomic layers, and wherein forming the nitrogen-doped silicon oxide layer includes forming nitrogen in the nitrogen-doped silicon oxide layer that does not inhibit silicidation.
6. The method of claim 5 , wherein annealing the refractory metal layer to form the nitride layer includes annealing the refractory metal layer to form the nitride layer having a thickness of approximately less than 20 to 50 angstroms.
7. The method of claim 5 , wherein forming the bottom silicon layer comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
8. The method of claim 5 , wherein annealing the refractory metal layer to form the refractory metal silicide conductor layer concurrently forms the nitride layer interposed between the bottom silicon layer and the refractory metal silicide conductor layer.
9. The method of claim 5 , wherein annealing the refractory metal layer to form the nitride layer includes annealing the refractory metal layer to form the nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms.
10. The method of claim 5 , wherein annealing the refractory metal layer to form the nitride layer includes annealing the refractory metal layer to form the nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms.
11. A method of forming a semiconductor memory device, comprising: forming a plurality of memory cells; coupling a plurality of access transistors to the plurality of memory cells; and coupling at least one word line formed over a gate oxide layer to the plurality of access transistors by a method comprising: forming a bottom silicon layer over the gate oxide layer; forming a silicon oxide layer over the bottom silicon layer; annealing the silicon oxide layer in a nitrogen-containing ambient to form a nitrogen-doped silicon oxide layer, wherein annealing the silicon oxide layer in the nitrogen-containing ambient to form the nitrogen-doped silicon oxide layer includes forming the nitrogen-doped silicon oxide layer doped with nitrogen so as not to inhibit subsequent silicidation; forming a titanium layer on the nitrogen-doped silicon oxide layer; and annealing the titanium layer to form a titanium silicide conductor layer and a thin, silicon nitride layer having a low nitrogen concentration of approximately 10 13 ions/cm 3 interposed between the bottom silicon layer and a refractory metal silicide conductor layer, wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a thickness of a few atomic layers.
12. The method of claim 11 , wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms.
13. The method of claim 11 , wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms.
14. The method of claim 11 , wherein annealing the titanium layer to form the titanium silicide conductor layer concurrently forms the silicon nitride layer interposed between the bottom silicon layer and the titanium silicide conductor layer.
15. The method of claim 11 , wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a thickness of approximately less than 20 to 50 angstroms.
16. A method of forming a semiconductor memory device, comprising: forming a plurality of memory cells; coupling a plurality of access transistors to the plurality of memory cells; and coupling at least one word line formed over a gate oxide layer to the plurality of access transistors by a method comprising: forming a bottom silicon layer over the gate oxide layer; forming a silicon oxide layer over the bottom silicon layer; annealing the silicon oxide layer in a nitrogen-containing ambient to form a nitrogen-doped silicon oxide layer, wherein annealing the silicon oxide layer in the nitrogen-containing ambient to form the nitrogen-doped silicon oxide layer includes forming the nitrogen-doped silicon oxide layer doped with nitrogen so as not to inhibit subsequent silicidation; forming a titanium layer on the nitrogen-doped silicon oxide layer; annealing the titanium layer to form a titanium silicide conductor layer and a thin, silicon nitride layer having a low nitrogen concentration of approximately 10 13 ions/cm 3 interposed between the bottom silicon layer and a refractory metal silicide conductor layer, wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a thickness of a few atomic layers; forming a cap dielectric over the titanium silicide conductor layer; etching each layer to define a word line stack; and forming spacers alongside the word line stack.
17. The method of claim 16 , wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a thickness of approximately less than 20 to 50 angstroms.
18. The method of claim 16 , wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms.
19. The method of claim 16 , wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms.
20. A method of forming a semiconductor memory device, comprising: forming a plurality of memory cells; coupling a plurality of access transistors to the plurality of memory cells; coupling at least one word line formed over a gate oxide layer to the plurality of access transistors by a method comprising: forming a bottom silicon layer over the gate oxide layer; forming a nitrogen-doped silicon oxide layer over the bottom silicon layer; forming a titanium layer on the nitrogen-doped silicon oxide layer; and forming a titanium nitride cap over the titanium layer; and annealing the titanium layer, after forming the titanium nitride cap, to form a titanium silicide conductor layer and a thin, silicon nitride layer having a low nitrogen concentration of approximately 10 13 ions/cm 3 from the nitrogen-doped silicon oxide layer and the titanium layer, wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a thickness of a few atomic layers interposed between the bottom silicon layer and the titanium silicide conductor layer.
21. The method claim 20 , wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a thickness of approximately less than 20 to 50 angstroms.
22. The method of claim 20 , wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms.
23. The method of claim 20 , wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms.
24. A method of forming a semiconductor memory device, comprising: forming a plurality of memory cells; coupling a plurality of access transistors to the plurality of memory cells; and coupling at least one word line to the plurality of access transistors, wherein the at least one word line comprises: coupling a bottom silicon layer to a gate oxide layer; coupling a thin, nitride layer to the bottom silicon layer; and coupling a refractory metal silicide layer produced from a reaction of the refractory metal layer and a nitrogen-doped silicon oxide layer to the nitride layer having a low nitrogen concentration of approximately 10 13 ions/cm 3 , wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a residual of the nitrogen-doped silicon oxide layer after the reaction with the refractory metal layer, and wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a thickness of a few atomic layers and increases resistance of the at least one word line by a factor of not more than two.
25. The method of claim 24 , wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a thickness of approximately less than 20 to 50 angstroms.
26. The method of claim 24 , wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms.
27. The method of claim 24 , wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms.
28. A method of forming a semiconductor memory device, comprising: forming a plurality of memory cells; coupling a plurality of access transistors to the plurality of memory cells; and coupling at least one word line to the plurality of access transistors, wherein the at least one word line comprises: coupling a bottom silicon layer to a gate oxide layer; forming a refractory metal silicide layer produced from a reaction of a refractory metal layer and a nitrogen-doped silicon oxide layer; and interposing a silicon nitride layer having a low nitrogen concentration of approximately 10 13 ions/cm 3 between the refractory metal silicide layer and the bottom silicon layer, wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a residual of the nitrogen-doped silicon oxide layer after the reaction with the refractory metal layer, and wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a thickness of a few atomic layers and increases resistance of the at least one word line by a factor of not more than two.
29. The method of claim 28 , wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a thickness of approximately less than 20 to 50 angstroms.
30. The method of claim 28 , wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms.
31. The method of claim 28 , wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms.
32. A method of forming a semiconductor transistor structure, comprising: forming a substrate; coupling a gate oxide layer to the substrate; coupling a bottom silicon layer to the gate oxide layer; coupling a silicon nitride layer to the bottom silicon layer; and coupling a refractory metal silicide layer produced from a reaction of a refractory metal layer and a nitrogen-doped silicon oxide layer to the silicon nitride layer having a low nitrogen concentration of approximately 10 13 ions/cm 3 , wherein coupling the refractory metal silicide layer to the silicon nitride layer includes coupling the refractory metal silicide layer to the silicon nitride layer having a residual of the nitrogen-doped silicon oxide layer after the reaction with the refractory metal layer, and wherein coupling the refractory metal silicide layer to the silicon nitride layer includes coupling the refractory metal silicide layer to the silicon nitride layer having a thickness of a few atomic layers and increases a resistance of the structure by a factor of not more than two.
33. The method of claim 32 , wherein coupling the refractory metal silicide layer to the silicon nitride layer includes coupling the refractory metal silicide layer to the silicon nitride layer having a thickness of approximately less than 20 to 50 angstroms.
34. The method of claim 32 , wherein coupling the refractory metal silicide layer to the silicon nitride layer includes coupling the refractory metal silicide layer to the silicon nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms.
35. The method of claim 32 , wherein coupling the refractory metal silicide layer to the silicon nitride layer includes coupling the refractory metal silicide layer to the silicon nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms.
36. A method of forming a semiconductor transistor structure, comprising: forming a substrate; coupling a gate oxide layer to the substrate; coupling a bottom silicon layer to the gate oxide layer; coupling a nitride layer to the bottom silicon layer; coupling a refractory metal silicide layer produced from a reaction of a refractory metal layer and a nitrogen-doped silicon oxide layer to the nitride layer having a low nitrogen concentration of approximately 10 13 ions/cm 3 , wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a residual of the nitrogen-doped silicon oxide layer after the reaction with the refractory metal layer, and wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a thickness of a few atomic layers and increases a resistance of the structure by a factor of not more than two; coupling a dielectric layer to the refractory metal silicide layer; stacking the gate oxide layer, the bottom silicon layer, the nitride layer, the refractory metal silicide layer and the dielectric layer; coupling at least one oxide spacer alongside the stack; and forming two source/drain regions in the substrate and adjacent the at least one oxide spacer.
37. The method of claim 36 , wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a thickness of approximately less than 20 to 50 angstroms.
38. The method of claim 36 , wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms.
39. The method of claim 36 , wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms.
40. A method of forming a semiconductor transistor structure, comprising: forming a substrate; coupling a gate oxide layer to the substrate; coupling a bottom silicon layer to the gate oxide layer; forming a refractory metal silicide layer, wherein forming the refractory metal silicide layer includes forming the refractory metal silicide layer having a reaction of a refractory metal layer and a nitrogen-doped silicon oxide layer; and interposing a nitride layer having a low nitrogen concentration of approximately 10 13 ions/cm 3 between the refractory metal silicide layer and the bottom silicon layer, wherein interposing the nitride layer includes interposing the nitride layer having a residual of the nitrogen-doped silicon oxide layer after the reaction with the refractory metal layer and a thickness of a few atomic layers.
41. The method of claim 40 , wherein interposing the nitride layer includes interposing the nitride layer having a thickness of approximately less than 20 to 50 angstroms.
42. The method of claim 40 , wherein interposing the nitride layer includes interposing the nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms.
43. The method of claim 40 , wherein interposing the nitride layer includes interposing the nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms.
44. A method of forming a semiconductor transistor structure, comprising: forming a substrate; coupling a gate oxide layer coupled to the substrate; coupling a bottom silicon layer coupled to the gate oxide layer; coupling a refractory metal silicide layer, wherein coupling the refractory metal silicide layer includes coupling the refractory metal silicide layer produced from a reaction of a refractory metal layer and a nitrogen-doped silicon oxide layer; interposing a silicon nitride layer having a low nitrogen concentration of approximately 10 13 ions/cm 3 between the refractory metal silicide layer and the bottom silicon layer, wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a residual of the nitrogen-doped silicon oxide layer after the reaction with the refractory metal layer, and wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a thickness of a few atomic layers and increases a resistance of the structure by a factor of not more than two; coupling a dielectric layer to the refractory metal silicide layer; stacking the gate oxide layer, the bottom silicon layer, the nitride layer, the refractory metal silicide layer and the dielectric layer; coupling at least one oxide spacer alongside the stack; and forming two source/drain regions in the substrate and adjacent the at least one oxide spacer.
45. The method of claim 44 , wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a thickness of approximately less than 20 to 50 angstroms.
46. The method of claim 44 wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having the low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms.
47. The method of claim 44 , wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms.
48. A method of forming a semiconductor transistor structure, comprising: forming a semiconductor substrate; coupling a gate oxide layer to the semiconductor substrate; coupling a bottom silicon layer to the gate oxide layer; introducing a conductor layer adjacent to the bottom silicon layer; and interposing a thin, nitride layer having a thickness of a few atomic layers between the bottom silicon layer and the conductor layer so as not inhibit subsequent silicidation, and wherein interposing the nitride layer includes interposing the nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms.
49. The method of claim 48 , wherein interposing the nitride layer includes interposing the nitride layer having a thickness of approximately less than 20 to 50 angstroms.
50. The method of claim 48 , wherein coupling the bottom silicon layer comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
51. A method of forming a semiconductor transistor structure, comprising: forming a semiconductor substrate; coupling a gate oxide layer to the semiconductor substrate; coupling a bottom silicon layer to the gate oxide layer; introducing a conductor layer adjacent to the bottom silicon layer; and interposing a thin, nitride layer having a thickness of a few atomic layers between the bottom silicon layer and the conductor layer such as not to inhibit subsequent silicidation, wherein interposing the nitride layer includes interposing the nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms.
52. The method of claim 51 , wherein interposing the nitride layer includes interposing the nitride layer having a thickness of approximately less than 20 to 50 angstroms.
53. The method of claim 51 , wherein coupling the bottom silicon layer comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
54. A method of forming a semiconductor memory device, comprising: forming a plurality of memory cells; coupling a plurality of access transistors to the plurality of memory cells; and coupling at least one word line formed over a gate oxide layer to the plurality of access transistors by a method comprising: forming a bottom silicon layer over the gate oxide layer; forming a nitrogen-doped silicon oxide layer over the bottom silicon layer; forming a refractory metal layer on the nitrogen-doped silicon oxide layer; and annealing the refractory metal layer to form a refractory metal silicide conductor layer and a thin, nitride layer having a thickness of a few atomic layers interposed between the bottom silicon layer and the refractory metal silicide conductor layer, wherein during annealing of the refractory metal layer the nitrogen in the nitrogen-doped silicon oxide layer does not inhibit silicidation, and wherein annealing the refractory metal layer to form the nitride layer includes annealing the refractory metal layer to form the nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms.
55. The method of claim 54 , wherein forming the bottom silicon layer comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
56. The method of claim 54 , wherein annealing the refractory metal layer to form a refractory metal silicide conductor layer concurrently forms the nitride layer interposed between the bottom silicon layer and the refractory metal silicide conductor layer.
57. A method of forming a semiconductor memory device, comprising: forming a plurality of memory cells; coupling a plurality of access transistors to the plurality of memory cells; and coupling at least one word line formed over a gate oxide layer to the plurality of access transistors by a method comprising: forming a bottom silicon layer over the gate oxide layer; forming a nitrogen-doped silicon oxide layer over the bottom silicon layer; forming a refractory metal layer on the nitrogen-doped silicon oxide layer; and annealing the refractory metal layer to form a refractory metal silicide conductor layer and a thin, nitride layer having a thickness of a few atomic layers interposed between the bottom silicon layer and the refractory metal silicide conductor layer, wherein during annealing of the refractory metal layer the nitrogen in the nitrogen-doped silicon oxide layer does not inhibit silicidation, and wherein annealing the refractory metal layer to form the nitride layer includes annealing the refractory metal layer to form the nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms.
58. The method of claim 57 , wherein annealing the refractory metal layer to form the refractory metal silicide conductor layer concurrently forms the nitride layer interposed between the bottom silicon layer and the refractory metal silicide conductor layer.
59. The method of claim 57 , wherein annealing the refractory metal layer to form the nitride layer includes annealing the refractory metal layer to form the nitride layer having a thickness of approximately less than 20 to 50 angstroms.
60. A method of forming a semiconductor memory device, comprising: forming a plurality of memory cells; coupling a plurality of access transistors to the plurality of memory cells; and coupling at least one word line formed over a gate oxide layer to the plurality of access transistors by a method comprising: forming a bottom silicon layer over the gate oxide layer; forming a silicon oxide layer over the bottom silicon layer; annealing the silicon oxide layer in a nitrogen-containing ambient to form a nitrogen-doped silicon oxide layer, wherein forming the nitrogen-doped silicon oxide layer includes forming the nitrogen-doped silicon oxide layer with nitrogen so as not to inhibit subsequent silicidation; forming a titanium layer on the nitrogen-doped silicon oxide layer; and annealing the titanium layer to form a titanium silicide conductor layer and a thin, silicon nitride layer having a thickness of a few atomic layers interposed between the bottom silicon layer and a refractory metal silicide conductor layer; wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms.
61. The method of claim 60 , wherein annealing the titanium layer to form a titanium silicide conductor layer concurrently forms the silicon nitride layer interposed between the bottom silicon layer and the titanium silicide conductor layer.
62. The method of claim 60 , wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a thickness of approximately less than 20 to 50 angstroms.
63. A method of forming a semiconductor memory device, comprising: forming a plurality of memory cells; coupling a plurality of access transistors to the plurality of memory cells; and coupling at least one word line formed over a gate oxide layer to the plurality of access transistors by a method comprising: forming a bottom silicon layer over the gate oxide layer; forming a silicon oxide layer over the bottom silicon layer; annealing the silicon oxide layer in a nitrogen-containing ambient to form a nitrogen-doped silicon oxide layer, wherein forming the nitrogen-doped silicon oxide layer includes forming the nitrogen-doped silicon oxide layer that is doped with nitrogen so as not to inhibit subsequent silicidation; forming a titanium layer on the nitrogen-doped silicon oxide layer; and annealing the titanium layer to form a titanium silicide conductor layer and a thin, silicon nitride layer having a thickness of a few atomic layers interposed between the bottom silicon layer and a refractory metal silicide conductor layer, wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms.
64. The method of claim 63 , wherein forming the bottom silicon layer comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
65. The method of claim 63 , wherein annealing the silicon oxide layer in the nitrogen-containing ambient includes selecting a nitrogen-containing ambient from at least one material selected from the group consisting of N 2 O, NO and NH 3 .
66. A method of forming a semiconductor memory device, comprising: forming a plurality of memory cells; coupling a plurality of access transistors to the plurality of memory cells; and coupling at least one word line over a gate oxide layer to the plurality of access transistors by a method comprising: forming a bottom silicon layer over the gate oxide layer; forming a silicon oxide layer over the bottom silicon layer; annealing the silicon oxide layer in a nitrogen-containing ambient to form a nitrogen-doped silicon oxide layer, wherein annealing the silicon oxide layer in the nitrogen-containing ambient includes doping the nitrogen-containing ambient with nitrogen so as not to inhibit subsequent silicidation; forming a titanium layer on the nitrogen-doped silicon oxide layer; annealing the titanium layer to form a titanium silicide conductor layer and a thin, silicon nitride layer having a thickness of a few atomic layers interposed between the bottom silicon layer and a refractory metal silicide conductor layer, wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms; forming a cap dielectric over the titanium silicide conductor layer; etching each layer to define a word line stack; and forming spacers alongside the word line stack.
67. The method of claim 66 , wherein annealing the titanium layer to form the titanium silicide conductor layer concurrently forms the silicon nitride layer interposed between the bottom silicon layer and the titanium silicide conductor layer.
68. The method of claim 66 , wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a thickness of approximately less than 20 to 50 angstroms.
69. A method of forming a semiconductor memory device, comprising: forming a plurality of memory cells; coupling a plurality of access transistors to the plurality of memory cells; and coupling at least one word line to the plurality of access transistors, wherein the at least one word line is formed over a gate oxide layer by a method comprising: forming a bottom silicon layer over the gate oxide layer; forming a silicon oxide layer over the bottom silicon layer; annealing the silicon oxide layer in a nitrogen-containing ambient to form a nitrogen-doped silicon oxide layer, wherein annealing the silicon oxide layer in the nitrogen-containing ambient to form the nitrogen-doped silicon oxide layer includes forming the nitrogen-doped silicon oxide layer doped with nitrogen so as not to inhibit subsequent silicidation; forming a titanium layer on the nitrogen-doped silicon oxide layer; annealing the titanium layer to form a titanium silicide conductor layer and a silicon nitride layer having a thickness of a few atomic layers interposed between the bottom silicon layer and the refractory metal silicide conductor layer, wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms; forming a cap dielectric over the titanium silicide conductor layer; etching each layer to define a word line stack; and forming spacers alongside the word line stack.
70. The method of claim 69 , wherein annealing the silicon oxide layer in a nitrogen-containing ambient includes selecting the nitrogen-containing ambient from at least one material selected from the group consisting of N 2 O, NO and NH 3 .
71. The method of claim 69 , wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a thickness of approximately less than 20 to 50 angstroms.
72. A method of forming a semiconductor memory device, comprising: forming a plurality of memory cells; coupling a plurality of access transistors to the plurality of memory cells; and coupling at least one word line over a gate oxide layer to the plurality of access transistors by a method comprising: forming a bottom silicon layer over the gate oxide layer; forming a nitrogen-doped silicon oxide layer over the bottom silicon layer; forming a titanium layer on the nitrogen-doped silicon oxide layer; forming a titanium nitride cap over the titanium layer; and annealing the titanium layer, after forming the titanium nitride cap, to form a titanium silicide conductor layer and a silicon nitride layer having a thickness of a few atomic layers from the nitrogen-doped silicon oxide layer and the titanium layer, wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms interposed between the bottom silicon layer and the titanium silicide conductor layer.
73. The method of claim 72 , wherein forming the bottom silicon layer comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
74. The method of claim 72 , wherein annealing the titanium layer to form the titanium silicide conductor layer concurrently forms the silicon nitride layer interposed between the bottom silicon layer and the titanium silicide conductor layer.
75. A method of forming a semiconductor memory device, comprising: forming a plurality of memory cells; coupling a plurality of access transistors to the plurality of memory cells; and coupling at least one word line formed over a gate oxide layer to the plurality of access transistors by a method comprising: forming a bottom silicon layer over the gate oxide layer; forming a nitrogen-doped silicon oxide layer over the bottom silicon layer; forming a titanium layer on the nitrogen-doped silicon oxide layer; forming a titanium nitride cap over the titanium layer; and annealing the titanium layer, after forming the titanium nitride cap, to form a titanium silicide conductor layer and a thin, silicon nitride layer having a thickness of a few atomic layers from the nitrogen-doped silicon oxide layer and the titanium layer, wherein annealing the titanium layer to form the silicon nitride layer includes annealing the titanium layer to form the silicon nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms interposed between the bottom silicon layer and the titanium silicide conductor layer.
76. The method of claim 75 , wherein forming the bottom silicon layer comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
77. The method of claim 75 , wherein annealing the titanium layer to form the titanium silicide conductor layer concurrently forms the silicon nitride layer interposed between the bottom silicon layer and the titanium silicide conductor layer.
78. A method of forming a semiconductor memory device, comprising: forming a plurality of memory cells; coupling a plurality of access transistors to the plurality of memory cells; coupling at least one word line to the plurality of access transistors, wherein the at least one word line comprises: coupling a bottom silicon layer to a gate oxide layer; coupling a thin, nitride layer to the bottom silicon layer; and coupling a refractory metal silicide layer produced from a reaction of the refractory metal layer and a nitrogen-doped silicon oxide layer to the nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms, wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a residual of the nitrogen-doped silicon oxide layer after the reaction with the refractory metal layer, and wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a thickness of a few atomic layers and increases resistance of the at least one word line by a factor of not more than two.
79. The method of claim 78 , wherein coupling the bottom silicon layer comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
80. The method of claim 78 , wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a thickness of approximately less than 20 to 50 angstroms.
81. A method of forming a semiconductor memory device, comprising: forming a plurality of memory cells; coupling a plurality of access transistors to the plurality of memory cells; coupling at least one word line to the plurality of access transistors, wherein the at least one word line comprises: coupling a bottom silicon layer to a gate oxide layer; coupling a thin, nitride layer to the bottom silicon layer; and coupling a refractory metal silicide layer produced from a reaction of a refractory metal layer and a nitrogen-doped silicon oxide layer to the nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms, wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer that is a residual of the nitrogen-doped silicon oxide layer after the reaction with the refractory metal layer, and wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a thickness of a few atomic layers and increases resistance of the at least one word line by a factor of not more than two.
82. The method of claim 81 , wherein coupling the bottom silicon layer comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
83. The method of claim 81 , wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a thickness of approximately less than 20 to 50 angstroms.
84. A method of forming a semiconductor memory device, comprising: forming a plurality of memory cells; coupling a plurality of access transistors to the plurality of memory cells; coupling at least one word line to the plurality of access transistors, wherein the at least one word line comprises: coupling a bottom silicon layer to a gate oxide layer; and forming a refractory metal silicide layer produced from a reaction of a refractory metal layer and a nitrogen-doped silicon oxide layer; and interposing a silicon nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms between the refractory metal silicide layer and the bottom silicon layer, wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a residual of the nitrogen-doped silicon oxide layer after the reaction with the refractory metal layer, and wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a thickness of a few atomic layers and increases resistance of the at least one word line by a factor of not more than two.
85. The method of claim 84 , wherein coupling the bottom silicon layer comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
86. The method of claim 84 , wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a thickness of approximately less than 20 to 50 angstroms.
87. A method of forming a semiconductor memory device, comprising: forming a plurality of memory cells; coupling a plurality of access transistors to the plurality of memory cells; coupling at least one word line to the plurality of access transistors, wherein the at least one word line comprises: coupling a bottom silicon layer to a gate oxide layer; and forming a refractory metal silicide layer produced from a reaction of a refractory metal layer and a nitrogen-doped silicon oxide layer; and interposing a silicon nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms between the refractory metal silicide layer and the bottom silicon layer, wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a thickness of a few atomic layers and increases resistance of the at least one word line by a factor of not more than two, and wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a residual of the nitrogen-doped silicon oxide layer after the reaction with the refractory metal layer.
88. The method of claim 87 , wherein coupling the bottom silicon layer comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
89. The method of claim 87 , wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a thickness of approximately less than 20 to 50 angstroms.
90. A method of forming a semiconductor transistor structure, comprising: forming a substrate; coupling a gate oxide layer to the substrate; coupling a bottom silicon layer to the gate oxide layer; coupling a silicon nitride layer to the bottom silicon layer; and coupling a refractory metal silicide layer produced from a reaction of a refractory metal layer and a nitrogen-doped silicon oxide layer to the silicon nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms, wherein coupling the refractory metal silicide layer to the silicon nitride layer includes coupling the refractory metal silicide layer to the silicon nitride layer having a residual of the nitrogen-doped silicon oxide layer after the reaction with the refractory metal layer, and wherein coupling the refractory metal silicide layer to the silicon nitride layer includes coupling the refractory metal silicide layer to the silicon nitride layer having a thickness of a few atomic layers and increases a resistance of the structure by a factor of not more than two.
91. The method of claim 90 , wherein coupling the bottom silicon comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
92. The method of claim 90 , coupling the refractory metal silicide layer to the silicon nitride layer includes coupling the refractory metal silicide layer to the silicon nitride layer having a thickness of approximately less than 20 to 50 angstroms.
93. A method of forming a semiconductor transistor structure, comprising: forming a substrate; coupling a gate oxide layer to the substrate; coupling a bottom silicon layer to the gate oxide layer; coupling a silicon nitride layer to the bottom silicon layer; and coupling a refractory metal silicide layer produced from a reaction of a refractory metal layer and a nitrogen-doped silicon oxide layer to the silicon nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms, wherein coupling the refractory metal silicide layer to the silicon nitride layer includes coupling the refractory metal silicide layer to the silicon nitride layer having a residual of the nitrogen-doped silicon oxide layer after the reaction with the refractory metal layer, and wherein coupling the refractory metal silicide layer to the silicon nitride layer includes coupling the refractory metal silicide layer to the silicon nitride layer having a thickness of a few atomic layers and increases a resistance of the structure by a factor of not more than two.
94. The method of claim 93 , wherein coupling the bottom silicon layer comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
95. The method of claim 93 , wherein coupling the refractory metal silicide layer to the silicon nitride layer includes coupling the refractory metal silicide layer to the silicon nitride layer having a thickness of approximately less than 20 to 50 angstroms.
96. A method of forming a semiconductor transistor structure, comprising: forming a substrate; coupling a gate oxide layer to the substrate; coupling a bottom silicon layer to the gate oxide layer; coupling a nitride layer to the bottom silicon layer; coupling a refractory metal silicide layer produced from a reaction of a refractory metal layer and a nitrogen-doped silicon oxide layer to the nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms, wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a residual of the nitrogen-doped silicon oxide layer after the reaction with the refractory metal layer, and wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a thickness of a few atomic layers and increases a resistance of the structure by a factor of not more than two; coupling a dielectric layer to the refractory metal silicide layer; stacking the gate oxide layer, the bottom silicon layer, the nitride layer, the refractory metal silicide layer and the dielectric layer; coupling at least one oxide spacer alongside the stack; and forming two source/drain regions in the substrate and adjacent the at least one oxide spacer.
97. The method of claim 96 , wherein coupling the bottom silicon layer comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
98. The method of claim 96 , wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a thickness of approximately less than 20 to 50 angstroms.
99. A method of forming a semiconductor transistor structure, comprising: forming a substrate; coupling a gate oxide layer to the substrate; coupling a bottom silicon layer to the gate oxide layer; coupling a nitride layer to the bottom silicon layer; coupling a refractory metal silicide layer produced from a reaction of a refractory metal layer and a nitrogen-doped silicon oxide layer to the nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms, wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a residual of the nitrogen-doped silicon oxide layer after the reaction with the refractory metal layer, and wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a thickness of a few atomic layers and increases a resistance of the structure by a factor of not more than two; coupling a dielectric layer to the refractory metal silicide layer; stacking the gate oxide layer, the bottom silicon layer, the nitride layer, the refractory metal silicide layer and the dielectric layer; coupling at least one oxide spacer alongside the stack; and forming two source/drain regions in the substrate and adjacent the at least one oxide spacer.
100. The method of claim 99 , wherein coupling the bottom silicon layer comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
101. The method of claim 99 , wherein coupling the refractory metal silicide layer to the nitride layer includes coupling the refractory metal silicide layer to the nitride layer having a thickness of approximately less than 20 to 50 angstroms.
102. A method of forming a semiconductor transistor structure, comprising: forming a substrate; coupling a gate oxide layer to the substrate; coupling a bottom silicon layer to the gate oxide layer; forming a refractory metal silicide layer produced from a reaction of a refractory metal layer and a nitrogen-doped silicon oxide layer; and interposing a nitride layer having a thickness of a few atomic layers and a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms between the refractory metal silicide layer and the bottom silicon layer, wherein interposing the nitride layer includes interposing the nitride layer having a residual of the nitrogen-doped silicon oxide layer after the reaction with the refractory metal layer.
103. The method of claim 102 , wherein coupling the bottom silicon layer comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
104. The method of claim 102 , wherein interposing the nitride layer includes interposing the nitride layer having a thickness of approximately less than 20 to 50 angstroms.
105. A method of forming a semiconductor transistor structure, comprising: forming a substrate; coupling a gate oxide layer to the substrate; coupling a bottom silicon layer to the gate oxide layer; forming a refractory metal silicide layer produced from a reaction of a refractory metal layer and a nitrogen-doped silicon oxide layer; interposing a silicon nitride layer having a low nitrogen concentration of approximately 1.4 percent by volume of nitrogen atoms between the refractory metal silicide layer and the bottom silicon layer, wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a residual of the nitrogen-doped silicon oxide layer after the reaction with the refractory metal layer, wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a thickness of a few atomic layers and increases a resistance of the structure by a factor of not more than two; coupling a dielectric layer to the refractory metal silicide layer; stacking the gate oxide layer, the bottom silicon layer, the nitride layer, the refractory metal silicide layer and the dielectric layer; coupling at least one oxide spacer alongside the stack; and forming two source/drain regions in the substrate and adjacent the at least one oxide spacer.
106. The method of claim 105 , wherein coupling the bottom silicon layer comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
107. The method of claim 105 , wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a thickness of approximately less than 20 to 50 angstroms.
108. A method of forming a semiconductor transistor structure, comprising: forming a substrate; coupling a gate oxide layer to the substrate; coupling a bottom silicon layer to the gate oxide layer; forming a refractory metal silicide layer produced from a reaction of a refractory metal layer and a nitrogen-doped silicon oxide layer; interposing a silicon nitride layer having a low nitrogen concentration of approximately 5.4 percent by volume of nitrogen atoms between the refractory metal silicide layer and the bottom silicon layer, wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a residual of the nitrogen-doped silicon oxide layer after the reaction with the refractory metal layer, and wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a thickness of a few atomic layers and increases a resistance of the structure by a factor of not more than two; coupling a dielectric layer to the refractory metal silicide layer; stacking the gate oxide layer, the bottom silicon layer, the nitride layer, the refractory metal silicide layer and the dielectric layer; coupling at least one oxide spacer alongside the stack; and forming two source/drain regions in the substrate and adjacent the at least one oxide spacer.
109. The method of claim 108 , wherein coupling the bottom silicon layer comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
110. The method of claim 108 , wherein interposing the silicon nitride layer includes interposing the silicon nitride layer having a thickness of approximately less than 20 to 50 angstroms.
111. A method of forming a semiconductor structure, comprising: forming a substrate; coupling an oxide layer to the substrate; coupling a bottom silicon layer to the oxide layer; introducing a conductor layer adjacent to the bottom silicon layer; and interposing a nitride layer having a thickness of a few atomic layers and a low nitrogen concentration of approximately 10 13 ions/cm 3 between the bottom silicon layer and the conductor layer.
112. The method of claim 111 , wherein coupling the bottom silicon layer comprises selecting a material selected from the group consisting of intrinsic silicon, intrinsic polysilicon, doped silicon, and doped polysilicon.
113. The method of claim 111 , wherein interposing the nitride layer includes interposing the nitride layer comprising silicon nitride.
114. The method of claim 111 , wherein interposing the nitride layer includes interposing the nitride layer having a thickness of approximately less than 20 to 50 angstroms.
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June 30, 2004
May 3, 2005
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