An integrated circuit includes a processor and at least one module and provides registers required for the modules as well as access to these registers. By concentrating the required registers according to the invention in a central register bank, which like the processor and the modules is connected to a fast AMBA-AHB bus, several advantages are achieved: for one, faster access is possible to each register. For another, the placement of the registers and the routing for the registers is simplified. This in particular allows chip area to be saved, which leads to cost savings in manufacture and enables higher component density. Furthermore, a slow AMBA-APB bus has now become optional.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit, implemented as a system-on-chip, comprising a processor platform which comprises a processor, at least two modules and a register bank, which are linked together via a bus, the register bank including at least two control registers assigned to the at least two modules.
2. The integrated circuit according to claim 1 , wherein at least one of said two modules is implemented as a controller.
3. The integrated circuit according to claim 1 , wherein in the register bank all registers needed for the modules are centrally arranged.
4. The integrated circuit according to claim 1 , wherein one module is implemented as a ROM controller and the other module is implemented as a RAM controller.
5. The integrated circuit according to claim 1 , wherein the bus is implemented as an AMBA-AHB bus.
6. The integrated circuit according to claim 5 , wherein the processor is connected via an AHB wrapper to the AMBA-AHB bus.
7. The integrated circuit according to claim 6 , wherein in the processor platform at least one component is provided, which is connected via an AMBA-APB bus and a bridge to the AMBA-AHB bus.
8. An integrated circuit implemented as a system-on-chip, comprising a processor platform which comprises a processor, at least one module and a register bank, which are linked together via a bus, the register bank including at least one register assigned to the at least one module, wherein in the register bank all registers needed for the modules are centrally arranged.
9. The integrated circuit according to claim 8 , wherein the at least one module is implemented as a controller.
10. The integrated circuit according to claim 8 , wherein the register bank includes at least two control registers for at least two modules.
11. The integrated circuit according to claim 8 , wherein the processor platform includes a first module implemented as a ROM controller and a second module implemented as a RAM controller.
12. The integrated circuit according to claim 8 , wherein the bus is implemented as an AMBA-AHB bus.
13. The integrated circuit according to claim 12 , wherein the processor is connected via an AHB wrapper to the AMBA-AHB bus.
14. The integrated circuit according to claim 12 , wherein in the processor platform at least one component is provided, which is connected via an AMBA-APB bus and a bridge to the AMBA-AHB bus.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 20, 2002
May 17, 2005
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