Disclosed herein is an easy and well-integrated method of etching features to different depths in a crystalline substrate, such as a single-crystal silicon substrate. The method utilizes a specialized masking process and takes advantage of a highly selective etch process. The method provides a system of interconnected, variable depth reservoirs and channels. The plasma used to etch the channels may be designed to provide a sidewall roughness of about 200 nm or less. The resulting structure can be used in various MEMS applications, including biomedical MEMS and MEMS for semiconductor applications.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of etching variable depth features in a crystalline substrate, comprising the following steps, performed in the following order: a) providing a structure including, from top to bottom, a first patterned photoresist layer, a hard mask layer, and a crystalline substrate; b) pattern etching said hard mask layer by exposing said structure to a plasma generated from a first plasma source gas which selectively etches said hard mask layer relative to said crystalline substrate, whereby a plurality of openings are formed in said hard mask layer, and whereby portions of an upper surface of said crystalline substrate are exposed through said openings; c) removing said first photoresist layer; d) providing a second patterned photoresist layer overlying said structure, whereby a portion of said second patterned photoresist layer covers at least one opening formed in said hard mask layer; e) pattern etching said crystalline substrate using said second patterned photoresist layer as a mask, whereby at least one deep feature is formed in said crystalline substrate; f) removing said second photoresist layer; g) pattern etching said crystalline substrate using said patterned hard mask layer, by exposing said structure to a plasma generated from a second plasma source gas which selectively etches said crystalline substrate relative to said hard mask layer, whereby at least one shallow feature is formed in said crystalline substrate, and wherein a sidewall of said at least one shallow feature has a surface roughness of about 200 nm or less.
2. The method of claim 1 , wherein said crystalline substrate is single-crystal silicon.
3. The method of claim 1 , wherein said hard mask layer comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, chromium, aluminum, and copper.
4. The method of claim 2 , wherein said hard mask layer comprises silicon oxide.
5. The method of claim 4 , wherein said first plasma source gas which selectively etches said silicon oxide layer relative to said silicon substrate comprises CF 4 and CHF 3 .
6. The method of claim 2 , wherein said at least one deep feature is etched in step e) using a cyclic silicon etch/polymer deposition process.
7. The method of claim 4 , wherein said second plasma source gas which selectively etches said silicon substrate relative to said silicon oxide layer comprises SF 6 , HBr, and O 2 .
8. The method of claim 7 , wherein said second plasma source gas comprises about 10 to about 50 volume % SF 6 , about 10 to about 50 volume % HBr, and about 10 to about 50 volume % O 2 .
9. The method of claim 8 , wherein said second plasma source gas comprises about 25 to about 40 volume % SF 6 , about 25 to about 40 volume % HBr, and about 25 to about 40 volume % O 2 .
10. The method of claim 1 , wherein a sidewall of said at least one shallow feature has a roughness of about 100 nm or less.
11. The method of claim 10 , wherein a sidewall of said at least one shallow feature has a roughness of about 50 nm or less.
12. The method of claim 1 , wherein said at least one deep feature is etched to have a diameter within the range of about 100 μm to about 5 mm.
13. The method of claim 1 , wherein said at least one deep feature is etched to have a depth within the range of about 50 μm to about 500 μm.
14. The method of claim 1 , wherein said at least one deep feature is etched to have a sidewall profile angle within the range of about 45° to about 90°.
15. The method of claim 1 , wherein said at least one shallow feature is etched to have a width within the range of about 10 μm to about 100 μm.
16. The method of claim 1 , wherein said at least one shallow feature is etched to have a depth within the range of about 10 μm to about 100 μm.
17. The method of claim 1 , wherein said at least one shallow feature is etched to have a sidewall profile angle within the range of about 45° to about 90°.
18. The method of claim 1 , wherein said method further includes a finishing step h), comprising: h-1) filling said at least one deep feature and said at least one shallow feature with silicon oxide; h-2) planarizing said substrate surface; and h-3) immersing said substrate in an HF acid bath for a period of time ranging from about 10 seconds to about 240 seconds, whereby said silicon oxide is removed from said at least one deep feature and said at least one shallow feature.
19. The method of claim 1 , wherein said method is performed such that at least one deep feature connects with at least one shallow feature.
20. The method of claim 1 , wherein a final structure resulting from performance of said method is used as a mold in the production of biomedical MEMS devices.
21. A method of preparing a mold including at least one reservoir and at least one channel, for use in the production of biomedical MEMS devices, comprising the following steps, performed in the following order: a) providing a structure including, from top to bottom, a first patterned photoresist layer, a silicon oxide layer, and a silicon substrate; b) pattern etching said silicon oxide layer by exposing said structure to a plasma generated from a first source gas which selectively etches said silicon oxide layer relative to said silicon substrate, whereby a plurality of openings are formed in said silicon oxide layer, and whereby portions of an upper surface of said silicon substrate are exposed through said openings; c) removing said first photoresist layer; d) providing a second patterned photoresist layer overlying said structure, whereby a portion of said second patterned photoresist layer covers at least one opening formed in said silicon oxide layer; e) pattern etching said silicon substrate using said second patterned photoresist layer as a mask, whereby at least one reservoir is formed in said silicon substrate; f) removing said second photoresist layer; g) pattern etching said silicon substrate using said patterned silicon oxide layer as a mask, by exposing said structure to a plasma generated from a second source gas which selectively etches said silicon substrate relative to said silicon oxide layer, whereby at least one channel is formed in said silicon substrate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 18, 2002
May 31, 2005
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