A chip stack comprising a flex circuit which itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces. Disposed on the top surface of the substrate in spaced relation to each other are at least first and second top conductive patterns. Similarly, disposed on the bottom surface of the substrate in spaced relation to each other are at least first and second bottom conductive patterns. The first top and bottom conductive patterns are electrically connected to each other, as are the second top and bottom conductive patterns. At least one top chip package including a first packaged chip is electrically connected to the first top conductive pattern, with at least one bottom chip package including a second packaged chip being electrically connected to the second bottom conductive pattern. The substrate is folded such that the second top conductive pattern is electrically connected to the top chip package.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a chip stack, comprising the steps of: (a) mounting at least one top chip package including a first packaged chip to a first top conductive pattern disposed on a top surface of a flexible substrate; (b) mounting at least one bottom chip package including a second packaged chip differing from the first packaged chip to a second bottom conductive pattern disposed on a bottom surface of the substrate; and (c) folding the substrate such that a second top conductive pattern disposed on the top surface and electrically connected to the second bottom conductive pattern is electrically connected to the top chip package.
2. The method of claim 1 wherein: step (a) comprises the substeps of: (i) mounting a first top chip package to the first top conductive pattern; and (ii) electrically connecting a second top chip package to the first top chip package; and step (c) comprises the substep of: (i) folding the substrate such that the second top conductive pattern is electrically connected to the second top chip package.
3. The method of claim 2 wherein: step (b) further comprises the substeps of: (i) mounting a first bottom chip package to the second bottom conductive pattern; and (ii) electrically connecting a second bottom chip package to a third bottom conductive pattern disposed on the bottom surface of the substrate; and step (c) further comprises the substeps of: (i) folding the substrate a first time such that the second top conductive pattern is electrically connected to the second top chip package; and (ii) folding the substrate a second time such that a third top conductive pattern disposed on the top surface and electrically connected to the third bottom conductive pattern is electrically connected to the first bottom chip package.
4. A method of forming a chip stack comprising the steps of: mounting one or more top BGA devices to a first top conductive pattern disposed along a top side of a flexible substrate; mounting one or more bottom BGA devices to a first bottom conductive pattern disposed along a bottom side of the flexible substrate; folding the flexible substrate such that a second top conductive pattern disposed along the top side and electrically connected to the first bottom conductive pattern is electrically connected to at least one of the one or more top BGA devices.
5. The method of claim 4 in which the one or more top BGA devices is associated with a corresponding keepout area oppositely situated along the bottom side of the flexible substrate, the keepout area having none of the one or more bottom BGA device mounted along it, such that no two BGA devices mounted are directly opposite each other.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 3, 2002
June 21, 2005
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