A method for testing a semiconductor memory device includes forcing the device into a logic state configuration that does not occur during normal operation of the device. The method may also include holding the logic state configuration for a user-variable length of time. In an embodiment, the device testing method includes flowing a direct current through a first input node of a bi-stable latch. This node may be electrically arranged between a node coupled to a voltage source and a node coupled to a circuit ground potential. An embodiment of a memory device may include testmode circuitry adapted to maintain a pair of bitlines at logic states that are not maintained during ordinary operation of the device. A system for testing a semiconductor memory device may include testmode circuitry adapted to force a pair of bitlines to the same logic state for a user-determined length of time.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory device comprising testmode circuitry, adapted to maintain a pair of bitlines coupled to a memory cell within the device to the same logic state during operation of the testmode circuitry by forwarding a direct current from a voltage source to each of the pair of bitlines through a path that comprises a respective local interconnect structure, wherein the bitlines are not maintained at the logic state during ordinary operation of the device.
2. The semiconductor memory device as recited in claim 1 , further comprising a user-determined voltage from the voltage source.
3. The semiconductor memory device as recited in claim 1 , wherein the direct currents flow for a user-determined time.
4. The semiconductor memory device as recited in claim 1 , wherein each of the local interconnect structures comprises at least one contact through which the respective direct current passes when the bitlines are at the same logic state.
5. The semiconductor memory device as recited in claim 1 , wherein the testmode circuitry is further adapted to force the pair of bitlines to circuit ground.
6. The semiconductor memory device as recited in claim 1 , wherein the testmode circuitry is further adapted to hold the bitlines at the same logic state for a user-determined length of time.
7. A system for testing a semiconductor memory device, said system comprising testmode circuitry within the semiconductor memory device adapted to maintain a pair of bitlines coupled to a memory cell within the memory device to the same logic state, wherein the bitlines are not maintained at the logic state during ordinary operation of the device.
8. Tho system as recited in claim 7 , wherein the testmode circuitry is adapted to force the pair of bitlines to a circuit ground potential.
9. The system as recited in claim 7 , wherein the testmode circuitry is further adapted to maintain the pair of bitlines at the same logic state for a user-determined length of time.
10. The system as recited in claim 7 , wherein the system is adapted to test a packaged memory device.
11. A method for testing a semiconductor memory device, said method comprising forcing the memory device into a logic state configuration not occurring during normal operation of the device by holding each of the bitlines at a circuit ground potential.
12. The method as recited in claim 11 , wherein said forcing comprises maintaining each of a pair of bitlines within the device at the same logic state, wherein the bitlines are complementary during normal operation of the device.
13. The method as recited in claim 11 , wherein said forcing comprises using circuitry external to the memory device.
14. The method as recited in claim 12 , wherein said forcing comprises flowing a direct current through the memory device from a voltage source to each of the pair of bitlines.
15. the method as recited in claim 14 , wherein flowing a direct current through the memory device comprises flowing a direct current through at least one local interconnect structure of a bi-stable latch.
16. The method as recited in claim 11 , wherein said forcing comprises holding the logic state configuration not occurring during normal operation of the device for a predetermined time.
17. The method as recited in claim 16 , wherein said predetermined time is user-variable.
18. The method as recited in claim 11 , said method further comprising performing a gross functional test on the memory device prior to said forcing.
19. The method as recited in claim 11 , said method further comprising performing a gross functional test on the memory device after said forcing.
20. A method of stressing a semiconductor memory device comprising passing a first direct current through a first input node of a bi-stable latch within the memory device.
21. The method as recited in claim 20 , wherein said passing the first direct current through the first input node comprises electrically coupling a first node within the memory device to a circuit ground potential and electrically coupling a second node within the memory device to a voltage source, wherein the first input node is arranged electrically between the first and second nodes.
22. The method as recited in claim 20 , said method further comprising passing a second direct current through a second input node of a bi-stable latch within the memory device.
23. The method as recited in claim 22 , wherein said passing the second direct current through the second input node comprises electrically coupling a third node within the memory device to a circuit ground potential and electrically coupling a fourth node within the memory device to a voltage source, wherein the second input node is arranged electrically between the third and fourth nodes.
24. The method as recited in claim 20 , wherein the memory device comprises an SRAM.
25. The method as recited in claim 20 , wherein said passing the direct current through the memory device occurs after packaging the device.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 9, 2001
June 21, 2005
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