Disclosed is a method of manufacturing a MOS transistor having an enhanced reliability. A passivation layer is formed on a gate electrode and on a substrate to prevent a generation of a recess on the substrate. After a mask pattern is formed on the substrate for masking a portion of the substrate, impurities are implanted into an exposed portion of the substrate to form source and drain regions. The substrate is rinsed so that the passivation layer or a recess-prevention layer is substantially entirely or partially removed while the mask pattern is substantially completely removed, thereby forming the MOS transistor. Therefore, the generation of the recess in the source and drain region of the substrate can be prevented due to the passivation layer during rinsing of the substrate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a metal oxide semiconductor transistor comprising: forming a gate electrode on a substrate, the gate electrode including a gate insulation pattern and a conductive pattern; forming a re-oxidation film on the gate electrode and on the substrate for curing the gate electrode and the substrate; forming a passivation layer on the gate electrode and on the substrate; forming a mask pattern for masking a portion of the substrate on which the passivation layer is formed, the unmasked portion forming an exposed portion of the substrate; forming a source and drain region by implanting impurity ions into the exposed portion of the substrate; cleaning the substrate to at least partially remove the passivation layer and substantially completely removing the mask pattern; forming a silicon oxide film on the sidewall of the gate electrode after removing the passivation layer; and forming a nitride spacer on the sidewall of the gate electrode on which the silicon oxide film is formed, the nitride spacer acting as a mask for implanting impurities into exposed portions of the substrate.
2. The method of forming a metal oxide semiconductor transistor of claim 1 , wherein the passivation layer is substantially completely removed.
3. The method of forming a metal oxide semiconductor transistor of claim 1 , wherein a solution which is employed for cleaning the substrate comprises sulfuric acid, a mixture of ammonia and hydrogen peroxide, or a mixture of sulfuric acid, ammonia and hydrogen peroxide.
4. The method of forming a metal oxide semiconductor transistor of claim 1 , wherein the passivation layer includes an insulation layer having an etching rate with respect to the rate for cleaning the substrate of less than approximately 1 Å/minute.
5. The method of forming a metal oxide semiconductor transistor of claim 1 , wherein the passivation layer has a thickness of approximately 5 to 50 Å.
6. The method of forming a metal oxide semiconductor transistor of claim 1 , wherein the passivation layer is formed employing an atomic layer deposition process.
7. The method of forming a metal oxide semiconductor transistor of claim 1 , wherein the passivation layer is selected from the group consisting of a silicon nitride layer, a metal oxide layer and a silicon oxide layer.
8. The method of forming a metal oxide semiconductor transistor of claim 1 , wherein the re-oxidation film has a thickness of approximately 5 to 50 Å.
9. The method of forming a metal oxide semiconductor transistor of claim 1 , wherein the re-oxidation film is selected from the group consisting of a silicon oxide film and a metal oxide film.
10. The method of forming a metal oxide semiconductor transistor of claim 1 , wherein the source and the drain regions have depths of about 100 to 500 Å.
11. The method of forming a metal oxide semiconductor transistor of claim 1 , wherein the conductive pattern includes a polysilicon layer, a composite of a polysilicon layer and a metal silicide layer, or a composite of a polysilicon layer and a metal layer.
12. A method of forming a metal oxide semiconductor transistor, comprising: forming a gate electrode on a substrate the gate electrode including a gate insulation pattern and a conductive pattern; forming a passivation layer on the gate electrode and on the substrate; forming a mask pattern for masking a portion of the substrate on which the passivation layer is formed, the unmasked portion forming an exposed portion of the substrate; forming a source and drain region by implanting impurity ions into the exposed portion of the substrate; cleaning the substrate to at least partially remove the passivation layer and substantially completely removing the mask pattern; forming a silicon oxide film on a sidewall of the gate electrode after removing said passivation layer; forming a nitride spacer on the sidewall of the gate electrode on which the silicon oxide film is formed, the nitride spacer acting as a mask for implanting impurities into exposed portions of the substrate; and implanting impurities into the exposed portion of the substrate.
13. The method of forming a metal oxide semiconductor transistor of claim 12 , wherein the silicon oxide film includes a middle temperature oxide.
14. The method of forming a metal oxide semiconductor transistor of claim 12 , wherein the passivation layer is substantially completely removed.
15. The method of forming a metal oxide semiconductor transistor of claim 12 , wherein a solution which is employed for cleaning the substrate comprises sulfuric acid, a mixture of ammonia and hydrogen peroxide, or a mixture of sulfuric acid, ammonia and hydrogen peroxide.
16. The method of forming a metal oxide semiconductor transistor of claim 12 , wherein the passivation layer includes an insulation layer having an etching rate with respect to the rate for cleaning the substrate of less than approximately 1 Å/minute.
17. The method of forming a metal oxide semiconductor transistor of claim 12 , wherein the passivation layer has a thickness of approximately 5 to 50 Å.
18. The method of forming a metal oxide semiconductor transistor of claim 12 , wherein the passivation layer is formed employing an atomic layer deposition process.
19. The method of forming a metal oxide semiconductor transistor of claim 12 , wherein the passivation layer is selected from the group consisting of a silicon nitride layer, a metal oxide layer and a silicon oxide layer.
20. The method of forming a metal oxide semiconductor transistor of claim 12 , wherein the re-oxidation film has a thickness of approximately 5 to 50 Å.
21. The method of forming a metal oxide semiconductor transistor of claim 12 , wherein the re-oxidation film is selected from the group consisting of a silicon oxide film and a metal oxide film.
22. The method of forming a metal oxide semiconductor transistor of claim 12 , wherein the source and the drain regions have depths of about 100 to 500 Å.
23. The method of forming a metal oxide semiconductor transistor of claim 12 , wherein the conductive pattern includes a polysilicon layer, a composite of a polysilicon layer and a metal silicide layer, or a composite of a polysilicon layer and a metal layer.
24. A method of forming a metal oxide semiconductor transistor comprising: forming gate electrodes on a substrate, each of the gate electrodes including a gate insulation pattern and a conductive pattern; forming a passivation layer on the gate electrodes and on the substrate; forming a first mask pattern on the substrate wherein the first mask pattern selectively opens a first region of the substrate and masks a first covered portion of the substrate including the passivation layer formed thereon; implanting first impurities into an exposed portion of the first region of the substrate; etching the substrate so that the first mask pattern is substantially completely removed; forming a second mask pattern on the substrate wherein the second mask pattern selectively opens a second region of the substrate and masks a second covered portion of the substrate including the passivation layer formed thereon; implanting second impurities into an exposed portion of the second region of the substrate; cleaning the substrate so that the passivation layer at least partially remains on the substrate and the second mask pattern is substantially completely removed; forming a silicon oxide film on the sidewall of the gate electrode after removing the passivation layer; and forming a nitride spacer on the sidewall of the gate electrode on which the silicon oxide film is formed, the nitride spacer acting as a mask for implanting impurities into exposed portions of the substrate.
25. The method of forming a metal oxide semiconductor transistor of claim 24 , which further comprises: forming a silicon oxide film on the substrate prior to implanting said first impurities; selectively implanting the first impurities into the first region of the substrate; and selectively implanting the second impurities into the second region of the substrate.
26. The method of forming a metal oxide semiconductor transistor of claim 24 , wherein the passivation layer includes an insulation layer having an etching rate with respect to a solution employed during the cleaning of the substrate of less than approximately 1 Å/minute.
27. The method of forming a metal oxide semiconductor transistor of claim 24 , wherein the passivation layer has a thickness of approximately 5 to 50 Å.
28. The method of forming a metal oxide semiconductor transistor of claim 24 , wherein the passivation layer is formed employing an atomic layer deposition process.
29. The method of forming a metal oxide semiconductor transistor of claim 24 , wherein the passivation layer is selected from the group consisting of a silicon nitride layer and a metal oxide layer.
30. The method of forming a metal oxide semiconductor transistor of claim 29 , wherein the re-oxidation film has a thickness of approximately 5 to 50 Å.
31. The method of forming a metal oxide semiconductor transistor of claim 29 , wherein the re-oxidation film is selected from the group consisting of silicon oxide film and a metal oxide film.
32. The method of forming a metal oxide semiconductor transistor of claim 24 , further comprising forming a re-oxidation film on the gate electrode and on the substrate for curing the gate electrode and the substrate, wherein the re-oxidation film is formed before forming the passivation layer.
33. The method of forming a metal oxide semiconductor transistor of claim 24 , wherein the silicon oxide film includes a middle temperature oxide.
34. A method of forming a metal oxide semiconductor transistor, the method comprising: forming gate electrodes on a substrate, each of the gate electrodes including a gate insulation pattern and a conductive pattern; forming a passivation layer on the gate electrodes and on the substrate; forming a first mask pattern on the substrate wherein the first mask pattern selectively opens a first region of the substrate and masks a first covered portion of the substrate including the passivation layer formed thereon; implanting first impurities into an exposed portion of the first region of the substrate; cleaning the substrate so that the first mask pattern is substantially completely removed; forming a second mask pattern on the substrate wherein the second mask pattern selectively opens a second region of the substrate and masks a second covered portion of the substrate including the passivation layer farmed thereon; implanting second impurities into an exposed portion of the second region of the substrate; cleaning the substrate so that the passivation layer at least partially remains on the substrate and the second mask pattern is completely removed; forming a silicon oxide film on the gate electrodes and on the substrate prior to implanting said first impurities; forming nitride spacers on sidewalls of the gate electrodes where the silicon oxide film is formed prior to implanting said first impurities; selectively implanting the first impurities into the first region of the substrate; and selectively implanting the second impurities into the second region of the substrate.
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April 30, 2003
July 5, 2005
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