A present invention provides a system and method for avoiding memory hazards in a multi-threaded CPU which shares an L-1 data cache. The system includes a CPU and an AACAM. The AACAM is capable of copying memory addresses from the two or more threads being processed by the CPU. The method provides for comparing the AACAM memory address with the active threads to avoid memory hazards by thread switching before the memory hazard occurs.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A system for avoiding memory hazards, comprising: a Central Processing Unit configured to process only a single thread retrofitted to process a first thread and a second thread; a level one data cache resident in said Central Processing Unit, said level one cache configured to receive said first thread and said second thread; and an external active address content addressable memory external to said Central Processing Unit and coupled to said Central Processing Unit, said active address content addressable memory configured to copy at least one memory address from said first thread and said second thread.
2. The system of claim 1 wherein said active address content addressable memory is adjacent said central processing unit.
3. The system of claim 1 further comprising: a first store buffer and a first load buffer associated with said first thread provided by said central processing unit, said first store buffer having a first store memory address, and said first load buffer having a first load memory address; and a second store buffer and a second load buffer associated with said second thread, said second store buffer having a second store memory address, said second load buffer having a second load memory address.
4. The system of claim 3 wherein said active address content addressable memory comprises a first active address content addressable memory for storing at least one memory address from said first store buffer and at least one memory address from said first load buffer.
5. The system of claim 4 wherein said active address content addressable memory comprises a second active address content addressable memory for storing at least one memory address from said second store buffer and at least one memory address from said second load buffer.
6. The system of claim 5 further comprising logic in said active address content addressable memory configured to receive an address to be accessed by said second thread from said Central Processing Unit and compare said address to said at least one memory address stored in said first active address content addressable memory and to cause a thread switch responsive to a match between said at least one address in said first active address content addressable memory and said address to be accessed.
7. The system of claim 6 further comprising logic in said active address content addressable memory configured to receive an address to be accessed by said first thread from said Central Processing Unit and compare said address to said at least one memory address stored in said second active address content addressable memory and to cause a thread switch responsive to a match between said at least one address in said second active address content addressable memory and said address to be accessed.
8. A method for avoiding memory hazards in a Central Processing Unit retrofitted for concurrently processing multiple threads, comprising: modifying said central processing unit that is configured to process a single thread in a manner to configure said Central Processing Unit to process a first thread and a second thread; executing a first thread in said Central Processing Unit, said first thread using a first store buffer, a first load buffer, and a L-1 data cache; switching execution from said first thread to a second thread; copying at least one memory address from a one of said first store buffer and said first load buffer to an active address content addressable memory that is external to said Central Processing Unit and coupled to said Central Processing Unit having a first active address content addressable memory; executing said second thread in said Central Processing Unit, said second thread using a second store buffer, a second load buffer, and said L-1 data cache; transmitting a memory address being accessed by said second thread during execution from said Central Processing Unit to said active address content addressable memory; determining if there is a match between said at least one memory address in said first active address content addressable memory and said memory address being accessed by said second thread; and switching execution from said second thread to said first thread responsive to a determination that said match exists.
9. The method of claim 8 further comprising: switching execution from said second thread to said first thread; copying at least one memory address from a one of said second store buffer and said second load buffer to an active address content addressable memory is external to said Central Processing Unit and coupled to said Central Processing Unit having a second active address content addressable memory; executing said first thread in said Central Processing Unit, said second thread using said first store buffer, said first load buffer, and said L-1 data cache; transmitting a memory address being accessed by said first thread during execution from said Central Processing Unit to said active address content addressable memory; determining in said active address content addressable memory if there is a match between said at least one memory address in said second active address content addressable memory and said memory address being accessed by said first thread; and switching execution from said first thread to said second thread responsive to a determination that said match exists.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 3, 2000
July 5, 2005
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