A method of manufacturing a semiconductor wafer device, includes the steps of: (a) forming lower wiring patterns over a semiconductor wafer, the lower wiring patterns being connected to semiconductor elements in a circuit area; (b) forming an interlevel insulating film with a planarized surface over the semiconductor wafer, covering the lower wiring patterns and having a planarized surface; and (c) forming via conductors connected to the lower wiring patterns and wiring patterns disposed on the via conductors in the circuit area and conductor patterns corresponding to the wiring patterns in a peripheral area other than the circuit area, by embedding the via conductors, wiring patterns and conductor patterns in the interlevel insulating film, the conductive patterns being electrically isolated. The method can form a desired wiring structure and can prevent an increase of the percentage of defective devices in an effective wafer area.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor wafer device comprising: a semiconductor wafer comprising a circuit area disposed in a central area of said semiconductor wafer and a peripheral area disposed around said circuit area of said semiconductor wafer; a number of semiconductor elements formed in said circuit area; a circuit multi-layer wiring structure formed on said circuit area and comprising multi-layer wirings connected to said semiconductor elements and interlevel insulating films, at least some of said multi-layer wirings being damascene wirings including wiring patterns and via conductors embedded in respective ones of said interlevel insulating films; and a peripheral multi-layer structure formed on said peripheral area, comprising insulating films made of the same layers as said interlevel insulating films and having one or more trenches formed in respective one or ones of said insulating films, each of said trenches having opposing sidewalls and a bottom surface in an associated one of said insulating films, and a conductor pattern filling each of said trenches and made of a same material as said wiring patterns in an associated one of said interlevel insulating films and not having conductor patterns corresponding to said via conductors.
2. The semiconductor wafer device according to claim 1 , wherein: said interlevel insulating films include a first insulating layer having a lower dielectric constant than silicon oxide and formed over said semiconductor wafer in an area except said peripheral area, and a second insulating layer having a dielectric constant higher than said first insulating layer and formed on said first insulating layer and said device further comprises said second insulating layer or a layer of a same material as the conductor covering an outermost side wall of said first insulating layer.
3. A semiconductor wafer device, comprising: an underlying structure including a semiconductor wafer; a first insulating layer having a lower dielectric constant than silicon oxide, formed over said underlying structure in an area excepting a peripheral area of said underlying structure, and having a gradually decreasing thickness at its periphery; a second insulating layer having a dielectric constant higher than said first insulating layer and formed on said first insulating layer; grooves formed at least through said second insulating layer; patterns of conductor filled in said grooves; said second insulating layer or a layer of a same material as the conductor covering an outermost side wall of said first insulating layer, and wherein a multi-layer peripheral structure is formed on said peripheral area not formed with circuits, comprising one or more of said grooves and conductor patterns filling said grooves.
4. A semiconductor wafer device comprising: a semiconductor wafer comprising a circuit area disposed in a central area of said semiconductor wafer and a peripheral area of said semiconductor wafer not formed with circuits; a number of semiconductor elements formed in said circuit area; a circuit multi-layer wiring structure formed on said circuit area and comprising multi-layer wirings connected to said semiconductor elements and interlevel insulating films, said interlevel insulating films comprising a first interlevel insulating film having a wiring trench formed from an upper surface to an intermediate depth of said first interlevel insulating film, and a via hole formed from a bottom surface of said wiring trench to a bottom surface of said first interlevel insulating film, said multi-layer wirings including a damascene wiring including a wiring pattern filling said wiring trench, and a via conductor filling said via hole; and a peripheral multi-layer structure formed in said peripheral area, comprising insulating films made of extensions of said interlevel insulating films, including a first insulating film made of an extension of said first interlevel insulating film and having one or more trenches formed from an upper surface to an intermediate depth of said first insulating film, said peripheral multi- layer structure including a conductor pattern or patterns filling said one or more trenches and made of a same material as said wiring in the same layer and not having conductor patterns corresponding to said via conductor.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 13, 2001
September 6, 2005
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