An electronic module, substrate assembly, and fabrication method, the assembly providing thermal conduction between an electronic device to be cooled and an aqueous coolant, while maintaining physical separation between the coolant and electronic device. The assembly includes a substrate, one or more electronic devices to be cooled, and a multilayer, impermeable barrier. The multilayer barrier includes a first layer, providing mechanical support for a second layer. The second, thinner layer provides an impermeable barrier, and a high effective thermal conductivity path between an electronic device and a cooling fluid in contact with an upper surface of the second barrier layer. Mechanical stresses are minimized by appropriate material selection for the first layer, and a thin second layer. When incorporated into an electronic module assembly including a module cap, the substrate assembly provides physical separation between a cooling fluid introduced into the module cap, and both the substrate and electronic devices.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An electronic module substrate assembly comprising: a substrate; at least one electronic device assembly to be cooled, said at least one electronic device assembly having a semiconductor chip, said semiconductor chip being electrically connected to said substrate; a first passivation layer, said first passivation layer substantially occupying the volume adjacent to said at least one electronic device assembly; a second passivation layer, said second passivation layer being sealably affixed to said substrate at its periphery and providing an impermeable barrier, said second passivation layer further being thermally coupled to an upper surface of one or more of said at least one electronic device assembly.
2. The apparatus of claim 1 , further comprising one or more passive electronic devices connected to said substrate, said first passivation layer substantially occupying the volume around said one or more passive devices, said first passivation layer further covering an upper surface of said one or more passive devices.
3. The apparatus of claim 1 , wherein said first passivation layer is formed of material selected from the group consisting of silicones, acrylic elastomers, thermoplastic elastomers, thermoplastic copolymers, polysulfide polymers and polyurethanes, thermoplastic polyimides, photosensitive polyimides, polyethersulfones and epoxies.
4. The apparatus of claim 1 , wherein said first passivation layer comprises two or more sub-layers, said two or more sub-layers being composed of different materials.
5. The apparatus of claim 1 , wherein said second passivation layer is metal.
6. The apparatus of claim 1 , wherein said at least one electronic device assembly further comprises a spacer thermally bonded to an upper surface of said semiconductor chip.
7. The apparatus of claim 4 , wherein said first passivation layer substantially occupies a volume under said at least one electronic device assembly.
8. The apparatus of claim 5 , wherein said second passivation layer comprises two or more sub-layers, said two or more sub-layers being composed of different materials.
9. The apparatus of claim 5 , wherein said metal is selected from the group consisting of copper, chrome, gold, nickel, titanium, and alloys thereof.
10. The apparatus of claim 6 , having a plurality of said electronic device assemblies, each of said plurality of electronic device assemblies having one of said spacers thermally bonded to an upper surface of said semiconductor chip.
11. The apparatus of claim 6 , wherein said spacers are composed of a material selected from the group consisting of silicon, silicon carbide, aluminum nitride, and diamond.
12. The apparatus of claim 6 , wherein an upper surface of said spacer is greater in area than said upper surface of said semiconductor chip.
13. The apparatus of claim 10 , wherein said spacers vary in thickness according to the thickness of said semiconductor chips, thin spacers being attached to thick chips and thick spacers being attached to thin chips.
14. An electronic module comprising: a substrate; at least one electronic device assembly to be cooled, said at least one electronic device assembly having a semiconductor chip, said semiconductor chip being electrically connected to said substrate; a first passivation layer, said first passivation layer substantially occupying the volume adjacent to said at least one electronic device assembly; a second passivation layer, said second passivation layer being sealably affixed to said substrate at its periphery and providing an impermeable barrier, said second passivation layer further being thermally coupled to an upper surface of one or more of said at least one electronic device assembly; and a module cap sealably affixed to said substrate, said cap and said substrate forming a volume capable of containing a cooling fluid.
15. The apparatus of claim 14 , further comprising a cooling fluid.
16. The apparatus of claim 14 , wherein said module further comprises at least one fluid inlet and at least one fluid outlet.
17. The apparatus of claim 15 , wherein said cooling fluid is an aqueous fluid.
18. A method of passivating an electronic module substrate assembly, said electronic module substrate assembly having a substrate and at least one electronic device assembly, said method comprising the steps of: applying a first passivation layer, wherein the first passivation layer substantially occupies the volume adjacent to said at least one electronic device assembly; exposing an upper surface of said at least one electronic device assembly; depositing a second passivation layer over said first passivation layer and over said exposed device assembly upper surface, wherein said second passivation layer is sealably affixed to said substrate at its periphery and provides an impermeable barrier, and said second passivation layer is further thermally coupled to an upper surface of one or more of said at least one electronic device assembly.
19. The method of claim 18 , wherein said second passivation layer is metal.
20. The method of claim 18 , wherein said applying is performed uniformly over said electronic module substrate assembly.
21. The method of claim 18 , wherein said applying is performed selectively over said electronic module substrate assembly, excluding one or more of said at least one electronic device assemblies.
22. The method of claim 20 , wherein said exposing is selectively performed over said one or more electronic device assemblies.
23. The method of claim 20 , wherein said exposing is performed uniformly over said electronic module substrate assembly.
24. The method of claim 21 , wherein said applying and said exposing are performed substantially concurrently.
25. The method of claim 21 , wherein said applying is performed using a mold.
26. The method of claim 21 , wherein said applying is a controlled pour process.
27. The method of claim 22 , wherein said exposing is a photolithographic process.
28. The method of claim 22 , wherein said exposing is an etch process.
29. The method of claim 23 , wherein said one or more electronic device assemblies includes a spacer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 17, 2002
September 6, 2005
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