A method is provided for manufacturing a semiconductor device having a multilayer wiring structure in which at least one insulating film is formed with a set of conducting portions which are electrically connected to each other to have a surface area of no less than 500 μm2 and which include a wiring having a width of no more than 1.0 μm. The method includes a polishing step for flattening the conducting portions together with the insulating film by chemical mechanical polishing, a chemical cleaning step for cleaning the flattened surface of the insulating film with a cleaning liquid, and a rising step for removing the cleaning liquid using a rinsing liquid. The rinsing step is performed using water with a dissolved oxygen concentration decreased to no more than 6 ppm by weight as the rinsing liquid.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a semiconductor device having a multilayer wiring structure in which at least one insulating film is formed with conductor pattern which includes at least one set of conducting portions electrically connected to each other, said at least one set of conducting portions having a surface area of no less than 500 μm 2 , the method comprising: a polishing step for flattening the conducting portions together with the insulating film by chemical mechanical polishing; a chemical cleaning step for cleaning a flattened surface of the insulating film with a cleaning liquid; and a rinsing step for removing the cleaning liquid using a rinsing liquid, wherein the rinsing step is performed using water with a dissolved oxygen concentration decreased to no more than 6 ppm by weight as the rinsing liquid, and wherein the polishing step includes a first polishing treatment using a chemical slurry and a polishing tool, the polishing step further including a second polishing treatment using said polishing tool and water with a dissolved oxygen concentration decreased to no more than 6 ppm by weight.
2. The method of manufacturing a semiconductor device according to claim 1 , wherein the dissolved oxygen concentration of the water as the rinsing liquid is no more than 4 ppm by weight.
3. The method of manufacturing a semiconductor device according to claim 1 , wherein the conductor pattern is formed of Cu or a Cu alloy.
4. The method of manufacturing a semiconductor device according to claim 1 , wherein the set of conducting portions includes a pad, and a wiring directly connected to the pad.
5. The method of manufacturing a semiconductor device according to claim 4 , wherein the wiring of the conducting portions has a width of no more than 1.0 μm.
6. The method of manufacturing a semiconductor device according to claim 1 , wherein the set of the conducting portions of the one insulating film includes a plurality of wirings which are electrically connected to each other via a conductor pattern of an underlying insulating film.
7. The method of manufacturing a semiconductor device according to claim 6 , wherein each of the wirings has a width of no more than 1.0 μm.
8. The method of manufacturing a semiconductor device according to claim 1 , wherein the dissolved oxygen concentration of the water used in the second polishing treatment is no more than 4 ppm by weight.
9. A method of manufacturing a semiconductor device having a multilayer wiring structure in which at least one insulating film is formed with conductor pattern which includes at least one set of conducting portions electrically connected t each other, said at least one set of conducting portions having a surface area of no less than 500 μm 2 , the method comprising: an insulating film forming step for forming an insulating film on a substrate; a pattern forming step for forming a wiring groove and a connection hole in the insulating film; a conductor forming step for applying a metal material to the insulating film to fill the wiring groove and the connection hole with the metal material; a polishing step for polishing the metal material and the insulating film by chemical mechanical polishing so that the metal material filled in the wiring groove and the connection hole remains as conducting portions; a cleaning step for cleaning the polished insulating film and the conducting portions with a cleaning liquid; a rinsing step for removing the cleaning liquid with water with a dissolved oxygen concentration of no more than 6 ppm by weight; and a drying step for removing the water use in the rinsing step; and wherein the polishing step includes a first polishing treatment using a chemical slurry and a polishing tool, the polishing step further including a second polishing treatment using said polishing tool and water with a dissolved oxygen concentration decreased to no more than the 6 ppm by weight.
10. The method of manufacturing a semiconductor device according to claim 9 , wherein the dissolved oxygen concentration of the water as the rinsing liquid is no more than 4 ppm by weight.
11. The method of manufacturing a semiconductor device according to claim 9 , wherein the metal material is Cu or a Cu alloy.
12. The method of manufacturing a semiconductor device according to claim 9 , wherein the set of conducting portions includes a pad, and a wiring directly connected to the pad.
13. The method of manufacturing a semiconductor device according to claim 12 , wherein the wiring of the conducting portions has a width of no more than 1.0 μm.
14. The method of manufacturing a semiconductor device according to claim 9 , wherein the set of the conducting portions of the one insulating film includes a plurality of wirings which are electrically connected to each other via a conductor pattern of an underlying insulating film.
15. The method of manufacturing a semiconductor device according to claim 14 , wherein each of the wirings has a width of no more than 1.0 μm.
16. The method of manufacturing a semiconductor device according to claim 9 , wherein the dissolved oxygen concentration of the water used in the second polishing treatment is no more than 4 ppm by weight.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 23, 2002
September 13, 2005
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