A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory device comprising: a plurality of first wirings, each of which is located along a first direction with a first wiring pitch; a plurality of chalcogenide material layers, each of which is located along said first direction; a plurality of second wirings, each of which is connected with a corresponding one of said chalcogenide material layers, and is located over said corresponding one of said chalcogenide material layers and along said first direction; and a plurality of vertical transistors, each of which is formed over said corresponding one of said first wirings and under a corresponding one of said second wirings and is comprised of a source region, a drain region, a channel region sandwiched between said source region and said drain region, a gate insulating film formed on all sides of said channel region and a gate electrode formed on said gate insulating film and surrounding said all sides of said channel region, wherein said drain region is electrically connected with said corresponding one of said second wirings through corresponding one of said chalcogenide material layers, wherein said source region is electrically connected with said corresponding one of said first wirings, wherein gate electrodes of two adjacent ones of said vertical transistors in a second direction, which intersects perpendicularly with said first direction, are connected with each other, and wherein gate electrodes of two adjacent ones of said vertical transistors in said first direction are separated from each other.
2. A semiconductor memory device according to claim 1 , further comprising: a plurality of plugs, wherein said source region is electrically connected with said corresponding one of said first wirings through a corresponding one of said plugs.
3. A semiconductor memory device according to claim 1 , wherein a barrier film is formed between said chalcogenide material and said drain region.
4. A semiconductor memory device according to claim 3 , wherein said barrier film is one of TiAlN or oxide of TiAlN or WTi, or laminated films of either of TiAlN or oxide of TiAlN or WTi, or ITO.
5. A semiconductor memory device according to claim 1 , wherein an area of said chalcogenide material connected to said drain region is smaller than an area of said drain region.
6. A semiconductor memory device according to claim 1 , wherein a chalcogenide material includes at least antimony and tellurium.
7. A semiconductor memory device according to claim 1 , further comprising: a plurality of word lines, each of which extends along said second direction with a word line pitch and is comprised of said gate electrodes which are connected with each other in said second direction, wherein said first wiring pitch is smaller than said word line pitch.
8. A semiconductor memory device according to claim 7 , wherein said gate electrode is formed by a side wall surrounding said source region, said channel region and said drain region.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 25, 2004
September 20, 2005
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