An improved UART which has a number of channels, with each channel having a set of channel configuration registers. Each channel configuration register includes an interrupt source register. The interrupt source register has a multi-bit interrupt source code which is used to indicate the source of the interrupt. This code is chosen to be compatible with prior UART devices. The device also includes a bus interface, and a plurality of device configuration registers accessible through the bus interface by a user. One of the device configuration registers is an interrupt register which provides a user accessible code to indicate the interrupt source. The code used for the interrupt source is a compressed version of the multiple bit code used in the channel configuration interrupt source register. This compression allows more channels to be represented in a single register, while also conveying the interrupt source information quickly to the user. Since the device interrupt register in the configuration registers is for access by the user, rather than internal access by UART drivers, there is no need for compatibility with the prior UART drivers.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A universal asynchronous receiver transmitter (UART) comprising: a plurality of channels; a plurality of sets of channel configuration registers, with each set of channel configuration registers corresponding to one of said plurality of channels; one of said channel configuration registers for each channel being a channel interrupt source register encoding in a multiple bit code a source of an interrupt for that channel, said multiple bit code being compatible with previous UART devices; a bus interface; a plurality of device configuration registers coupled to said bus interface and accessible directly from a bus by a user; and one of said device configuration registers being a device interrupt register having a user accessible code for indicating an interrupt source for each of said channels, said user accessible code having fewer bits than said multiple bit code in said interrupt source register in said channel configuration registers.
2. The UART of claim 1 wherein said multiple bit code is five bits.
3. The UART of claim 1 wherein said user accessible code is three bits for each channel.
4. The UART of claim 1 further comprising a plurality of interrupt channel bits in said device interrupt register, each of said interrupt channel bits corresponding to one of said channels.
5. The UART of claim 1 wherein said device interrupt register is a 32 bit register, and said UART includes eight channels.
6. The UART of claim 1 further comprising a FIFO manager configured to convert said multiple bit code from said channel interrupt source registers into said user accessible code.
7. The UART of claim 1 wherein said bus is a PCI bus.
8. A universal asynchronous receiver transmitter (CART) comprising: at least eight channels; a plurality of sets of channel configuration registers, with each set of channel configuration registers corresponding to one of said eight channels; one of said channel configuration registers for each channel being a channel interrupt source register encoding in a five bit code a source of an interrupt for that channel, said five bit code being compatible with previous UART devices; a PCI bus interface; a plurality of device configuration registers coupled to said PCI bus interface and accessible directly from a PCI bus by a user; one of said device configuration registers being a 32 bit device interrupt register having a user accessible code for indicating an interrupt source for each of said channels, said user accessible code being three bit interrupt codes corresponding to said five bit codes in said interrupt source register in said channel configuration registers; and a plurality of interrupt channel bits in said device interrupt register, each of said interrupt channel bits corresponding to one of said channels.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 17, 2000
September 20, 2005
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.