A semiconductor package includes a semiconductor chip connected to lead frames by wires and outer leads protruding from the semiconductor package. At this time, the outer leads are connected to the lead frames and grooves into which the outer leads are inserted into are provided in the semiconductor package, wherein the grooves are connected the lead frames. In mounting a first and a second semiconductor package, the outer leads of the first semiconductor package are inserted into the grooves of the second semiconductor package.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor package comprising: a semiconductor chip electrically connected to lead frames; outer leads protruding from a surface of the semiconductor package through via holes formed thereat, wherein the outer leads are connected to metal lines and the metal lines are connected to the lead frames; and grooves formed at a surface of the semiconductor package to expose the metal lines, whereby outer leads of another semiconductor package are connected to the metal lines through the grooves.
2. The semiconductor package of claim 1 , wherein the outer leads are disposed opposite to the grooves.
3. The semiconductor package of claim 1 , wherein the semiconductor package is connected to another semiconductor package by inserting the outer leads of the semiconductor package into grooves of another semiconductor package.
4. A semiconductor package comprising: a semiconductor chip electrically connected to lead frames; and outer wires protruding from a surface of the semiconductor package, wherein the outer wires are connected to the semiconductor chip through via holes, metal lines and the lead frames connected to the metal lines, wherein the semiconductor package is connected to another semiconductor package by interconnecting the outer wires with outer wires of another semiconductor package.
5. The semiconductor package of claim 4 , further comprising supporting structures having a predetermined length, the supporting structures being provided on the surface from which the outer wires protrude.
6. The semiconductor package of claim 5 , wherein positioning holes are provided on another semiconductor package.
7. The semiconductor package of claim 6 , wherein the semiconductor package is connected to another semiconductor package by inserting the supporting structures of the semiconductor package into the positioning holes of another semiconductor package.
8. The semiconductor package of claim 7 , wherein the supporting structures have a length greater than a total length of the interconnected outer wires.
9. The semiconductor package of claim 6 , wherein the supporting structures are inserted into the positioning holes.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 30, 2003
September 27, 2005
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