A command user interface with via mask programmability includes a decoder with transistors selectively coupleable to one of an input or its complement. This is accomplished in one way by making vias in an appropriate location to allow interconnection of the appropriate contact and the gate of the transistor.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A programmable decoder, comprising: a first decoder section comprising: a plurality of transistors connected in series whose gates are selectively coupled to receive either an input or its complement from one of a pair of contacts; and a pair of contacts for each transistor, each contact coupled to the input or to the complement of the input through a via.
2. The programmable decoder of claim 1 , and further comprising an actuation transistor connected in series with the plurality of transistors, the actuation transistor enabling the plurality of transistors for a read of the plurality of transistors.
3. The programmable decoder of claim 1 , wherein the plurality of transistors comprises the same number of transistors as there are data inputs to the decoder.
4. The programmable decoder of claim 1 , wherein the first or the second contact is accessed by forming a via to the contact.
5. The programmable decoder of claim 1 , wherein at least one of the series of transistors is further selectively coupled to receive a supply voltage.
6. The programmable decoder of claim 1 , and further comprising: a second decoder section comprising: a second plurality of transistors connected in series whose gates are selectively coupled to receive either an input or its complement from one of a second pair of contacts; and a pair of contacts for each of the plurality of second transistors, each of the second pairs of contacts coupled to the input or to the complement of the input.
7. The programmable decoder of claim 6 , wherein the second decoder section is connected in series with the first decoder section.
8. The programmable decoder of claim 6 , wherein the second decoder section is connected in parallel with the first decoder section.
9. The programmable decoder of claim 8 , wherein each of the decoder sections decodes a particular different set of inputs.
10. The programmable decoder of claim 6 , wherein at least one of the second plurality of transistors is further selectively coupled to receive a supply voltage using its via.
11. The programmable decoder of claim 6 , and further comprising: a third decoder section comprising: a third plurality of transistors connected in series whose gates are selectively coupled to receive either an input or its complement from one of a third pair of contacts; and a pair of contacts for each of the third plurality of transistors, each of the third pairs of contacts coupled to the input or to the complement of the input.
12. The programmable decoder of claim 11 , wherein the third decoder section is connected in series with the first and the second decoder sections.
13. The programmable decoder of claim 11 , wherein the third decoder section is connected in parallel with the first decoder and the second decoder sections.
14. The programmable decoder of claim 11 , wherein each of the decoder sections decodes a particular different set of inputs to the decoder.
15. The programmable decoder of claim 1 , wherein the first decoder section decodes data inputs to the programmable decoder.
16. The programmable decoder of claim 6 , wherein the first decoder section decodes data inputs to the programmable decoder and wherein the second decoder section decodes status inputs to the programmable decoder.
17. The programmable decoder of claim 11 , wherein the first decoder section decodes data inputs to the programmable decoder, and wherein the second decoder section decodes status inputs to the programmable decoder, and wherein the third decoder section decodes feedback inputs to the programmable decoder.
18. The decoder of claim 12 , wherein at least one of the third plurality of transistors is selectively coupled to a supply voltage.
19. A programmable decoder having a first input and a second input, comprising: a first decoder section coupled to decode data from the first input, the first decoder section comprising: a plurality of transistors connected in series; and a plurality of contacts, each contact coupled to either the input or the complement of the input, wherein the vias connect a gate of a single transistor of the plurality of transistors to either the input or to the complement of the input; and a second decoder section substantially identical to the first decoder section, and connected in series with the first decoder section, the second decoder section coupled to decode data from the second input.
20. The programmable decoder of claim 19 , and further comprising a plurality of latches to latch input and output data for the programmable decoder, wherein the plurality of latches comprises: a plurality of input latches to receive input data and a clock signal and to output latched input data to the decoder; a plurality of output latches to receive output data from a read only memory; and a plurality of status latches to receive state information from the read only memory and to output latched status data to the decoder.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 7, 2003
September 27, 2005
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