One embodiment of the present invention includes a microcontroller that enables its on-chip microprocessor to write data into a register of an on-chip programmable analog circuit even though the two circuits may be operating at different frequencies. Specifically, the microcontroller includes a write synchronization circuit that helps facilitate the write operation between these two circuits. For example, the write synchronization circuit is coupled to receive write cycle signals from the microprocessor and is also coupled to receive trigger signals based on a clocking signal received by the programmable analog circuit. Therefore, upon receiving a write cycle signal, the write synchronization circuit has the ability (if needed) to stall the microprocessor's operations until the optimum time for writing data into the register for controlling the programmable analog circuit. As such, the write synchronization circuit dynamically synchronizes the microprocessor's write operation with the programmable analog circuit's optimum timing condition for receiving data.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method comprising: (a) a microprocessor initiating a write cycle to store data into a register of an analog circuit, said analog circuit operating on a first clock signal of a first rate and said microprocessor operating on a second clock signal of a second rate; (b) asserting a signal to halt operation of said microprocessor until a predefined time frame of said first clock signal, wherein said predefined time frame is advantageous for storing data into said register of said analog circuit, wherein said predefined time frame does not comprise a settling time of said first clock signal; and (c) in response to said (b), said microprocessor storing said data into said register of said analog circuit.
2. The method as described in claim 1 wherein said analog circuit comprises a programmable circuit.
3. The method as described in claim 1 wherein said analog circuit comprises a switched-capacitor circuit.
4. The method as described in claim 1 wherein said signal halts said second clock signal.
5. The method as described in claim 1 wherein said predefined time frame comprises approximately an initial half cycle of an active cycle of said first clock signal.
6. The method as described in claim 1 wherein said microprocessor and said analog circuit are part of a microcontroller.
7. A system comprising: an analog circuit coupled to receive a first clock signal of a first rate; a microprocessor coupled to receive a second clock signal of a second rate and coupled to a register of said analog circuit, said microprocessor for transmitting a write cycle signal to store data into said register of said analog circuit; and a synchronization circuit coupled to receive said first clock signal and said write cycle signal and for asserting a signal to halt operation of said microprocessor until a predefined time frame of said first clock signal, wherein said predefined time frame is advantageous for storing data into said register of said analog circuit, wherein said predefined time frame does not comprise a settling time of said first clock signal.
8. The system as described in claim 7 wherein said analog circuit comprises a programmable circuit.
9. The system as described in claim 7 wherein said analog circuit comprises a switched-capacitor circuit.
10. The system as described in claim 7 wherein said signal halts said second clock signal.
11. The system as described in claim 7 wherein said predefined time frame comprises approximately an initial half cycle of an active cycle of said first clock signal.
12. The system as described in claim 7 wherein said system is part of a microcontroller.
13. A method comprising: (a) a microprocessor initiating a write cycle to store data into a register of an analog programmable circuit, said analog programmable circuit operating on a first clock signal of a first rate and said microprocessor operating on a second clock signal of a second rate; (b) a circuit asserting a signal to halt operation of said microprocessor until a predefined time frame of said first clock signal, wherein said predefined time frame is advantageous for storing data into said register of said analog programmable circuit, wherein said predefined time frame comprises approximately an initial half cycle of an active cycle of said first clock signal; and (c) in response to said (b), said microprocessor storing said data into said register of said analog programmable circuit.
14. The method as described in claim 13 wherein said analog programmable circuit comprises a switched-capacitor circuit.
15. The method as described in claim 13 wherein said signal halts said second clock signal.
16. The method as described in claim 13 wherein said predefined time frame does not comprise a settling time of said first clock signal.
17. The method as described in claim 13 wherein said microprocessor, said circuit and said analog programmable circuit are part of a microcontroller.
18. The method as described in claim 13 wherein said circuit is a write synchronization circuit.
19. The method as described in claim 1 wherein said first rate is different from said second rate.
20. The system as described in claim 7 wherein said first rate is different from said second rate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 25, 2001
September 27, 2005
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