Precompensation circuit for magnetic recording

1. A pre-compensation circuit for recording of data signals, comprising: a clock delay generator to generate clock delay data relative to a clock signal at a predetermined clock rate for each successive data signal to be recorded responsive to a pattern of adjacent data signals; n clock delay units to control recording times of the successive data signals, wherein n>=1, wherein each of the clock delay units operates to generate an output signal for determining the recording time of one data signal in each sequence of n successive data signals responsive to the clock delay data received by the clock delay unit for the one data signal in the sequence; a reference clock delay unit responsive to the clock signal for producing reference clock delay information at the predetermined clock rate; and a calibrator responsive to the reference clock delay information for calibrating each of the n clock delay units to a change in the predetermined clock rate.

2. The pre-compensation circuit of claim 1 , wherein a clock delay unit receives the clock delay data corresponding to a mth data signal of successive data signals in a clock period during which the clock delay unit that received the clock delay data corresponding to a (m−n+1)th data signal of the successive data signals generates the output signal for determining the recording time of a (m−n+1)th data signal.

3. The pre-compensation circuit of claim 1 , wherein each clock delay unit comprises a reprogrammable clock delay unit that is reprogrammed for the one data signal received in each sequence of successive data signals.

4. The pre-compensation circuit of claim 1 , wherein each pattern of adjacent data signals includes at least one of a pattern of data signals immediately preceding the data signal for which the clock delay data is generated and a set of data signals immediately succeeding the data signal for which the clock delay data is generated.

5. The pre-compensation circuit of claim 1 , wherein each pattern of adjacent data signals includes a pattern of data signals surrounding the data signal for which the clock delay data is generated.

6. The pre-compensation circuit of claim 1 , further comprising: a selector to select the output signals of the n clock delay units successively in each n data signal sequence to control the recording times of the successive data signals of the sequence so that the clock delay data for a mth data signal is received by one of the n clock delay units while the output signal of the clock delay unit that is to receive a (m+1)th data signal controls the recording time of a (m−n+1)th data signal.

7. The pre-compensation circuit of claim 1 , wherein the clock delay generator comprises: a look up table responsive to the pattern of adjacent data signals for forming clock delay data relative to the generated clock signal for each successive data signal.

8. The pre-compensation circuit of claim 1 , wherein the clock delay generator comprises: a look up table responsive to the pattern of adjacent data signals for each data signal to form clock delay information; and a combining unit to combine the reference clock delay information with the look up table formed clock delay information to generate the clock delay data for the data signal.

9. The pre-compensation circuit of claim 1 , wherein the reference clock delay unit comprises: a reprogrammable reference clock delay unit that is reprogrammed responsive to a change in the predetermined clock rate.

10. The pre-compensation circuit of claim 1 , wherein the calibrator comprises: a comparator for comparing the reference clock delay information to the output signals of the at least one clock delay unit to form an offset value for each clock delay unit.

11. The pre-compensation circuit of claim 1 , wherein each clock delay unit includes an interpolator for interpolating the clock delay data.

12. The pre-compensation circuit of claim 1 , wherein the at least one clock delay unit sequentially controls recording times of the successive data signals.

13. A method of pre-compensating recording of data signals, comprising the steps of: generating clock delay data relative to a clock signal at a predetermined clock rate for each successive data signal to be recorded responsive to a pattern of adjacent data signals; sequentially controlling recording times of the successive data signals by n clock delay units, wherein n>=1, wherein each of the clock delay units generates an output signal for determining the recording time of one data signal in each sequence of n successive data signals responsive to the clock delay data received by the clock delay unit for the one data signal of the sequence; producing reference clock delay information at the predetermined clock rate responsive to the clock signal; and calibrating each of the n clock delay units to a change in the predetermined clock rate responsive to the reference clock delay information.

14. The method of claim 13 , wherein a clock delay unit receives the clock delay data corresponding to a mth data signal of successive data signals in a clock period during which the clock delay unit that received the clock delay data corresponding to a (m−n+1)th data signal of the successive data signals generates the output signal for determining the recording time of the (m−n+1)th data signal.

15. The method of claim 13 , wherein each clock delay unit is reprogrammed for the one data signal received in each sequence of n successive data signals.

16. The method of claim 13 , wherein each pattern of adjacent data signals includes at least one of a pattern of data signals immediately preceding the data signal for which the clock delay data is generated and a set of data signals immediately succeeding the data signal for which the clock delay data is generated.

17. The method of claim 13 , wherein each pattern of adjacent data signals includes a pattern of data signals surrounding the data signal for which the clock delay data is generated.

18. The method of claim 13 , further comprising the step of: selecting the output signals of the n clock delay units successively in each n data signal sequence to control the recording times of the successive data signals of the sequence so that the clock delay data for a mth data signal is received by one of the n clock delay units while the output signal of the clock delay unit that is to receive a (m+1)th data signal controls the recording time of a (m−n+1)th data signal.

19. The method of claim 13 , wherein the step of generating the clock delay data comprises the step of: obtaining clock delay information from a look up table responsive to the pattern of adjacent data signals for forming clock delay data relative to the generated clock signal for each successive data signal.

20. The method of claim 13 , wherein the step of generating the clock delay data includes the steps of: obtaining clock delay information from a look up table responsive to the pattern of adjacent data signals for each data signal; and combining the reference clock delay information with the look up table formed clock delay information to generate the clock delay data for the data signal.

21. The method of claim 13 , wherein the reference clock delay information is re-calibrated responsive to the change in the predetermined clock rate.

22. The method of claim 13 , wherein the step of calibrating comprises the step of: comparing the reference clock delay information to the output signals of the at least one clock delay unit to form an offset value for each clock delay unit.

23. The method of claim 13 , wherein each clock delay unit interpolates the received clock delay data.

24. A pre-compensation circuit for recording of data signals, comprising: clock delay generating means for generating clock delay data relative to a clock signal at a predetermined clock rate for each successive data signal to be recorded responsive to a pattern of adjacent data signals; n clock delay means for controlling recording times of the successive data signals, wherein n>=1, wherein each of the clock delay means operates to generate an output signal for determining the recording time of one data signal in each sequence of n successive data signals responsive to the clock delay data received by the clock delay means in the sequence for the one data signal; a reference clock delay means responsive to the clock signal for producing reference clock delay information at the predetermined clock rate; and a calibration means responsive to the reference clock delay information for calibrating each of the n clock delay means to a change in the predetermined clock rate.

25. The pre-compensation circuit of claim 24 , wherein a clock delay means receives the clock delay data corresponding to a mth data signal of successive data signals in a clock period during which the clock delay means that received the clock delay data corresponding to a (m−n+1)th data signal of the successive data signals generates the output signal for determining the recording time of the (m−n+1)th data signal.

26. The pre-compensation circuit of claim 24 , wherein each clock delay means comprises: reprogrammable clock delay means that is reprogrammed for the one data signal received in each sequence of successive data signals.

27. The pre-compensation circuit of claim 24 , wherein each pattern of adjacent data signals includes at least one of a pattern of data signals immediately preceding the data signal for which the clock delay data is generated and a set of data signals immediately succeeding the data signal for which the clock delay data is generated.

28. The pre-compensation circuit of claim 24 , wherein each pattern of adjacent data signals includes a pattern of data signals surrounding the data signal for which the clock delay data is generated.

29. The pre-compensation circuit of claim 24 , further comprising: a selecting means for selecting the output signals of the n clock delay means successively in each n data signal sequence to control the recording times of the successive data signals of the sequence so that the clock delay data for a mth data signal is received by one of the n clock delay means while the output signal of the clock delay means that is to receive a (m+1)th data signal controls the recording time of a (m−n+1)th data signal.

30. The pre-compensation circuit of claim 24 , wherein the clock delay generating means comprises: means responsive to the pattern of adjacent data signals for looking up clock delay data relative to the generated clock signal for each successive data signal.

31. The pre-compensation circuit of claim 24 , wherein the clock delay generating means comprises: look up means responsive to the pattern of adjacent data signals for each data signal for forming clock delay information; and combining means for combining the reference clock delay information with the look up means formed clock delay information to generate the clock delay data for the data signal.

32. The pre-compensation circuit of claim 24 , wherein the reference clock delay means comprises: a reprogrammable reference clock delay means that is reprogrammed responsive to a change in the predetermined clock rate.

33. The pre-compensation circuit of claim 24 , wherein the calibration means comprises: a comparing means for comparing the reference clock delay information to the output signals of the at least one clock delay means to form an offset value for each clock delay means.

34. The pre-compensation circuit of claim 24 , wherein each clock delay means includes: interpolating means for interpolating the received clock delay data.

35. The pre-compensation circuit of claim 24 , wherein the at least one clock delay means sequentially controls recording times of the successive data signals.

36. In a pre-compensation circuit for recording of data signals, a computer usable medium having computer readable program units embodied therein comprising: a first program unit for determining clock delay data relative to a clock signal at a predetermined clock rate for each successive data signal to be recorded responsive to a pattern of adjacent data signals; a second program unit for controlling sequential operation of n programmable clock delay units to determine the recording time of the successive data signals, wherein n>=1, wherein each of the programmable clock delay units is controlled to generate an output signal for determining the recording time of one data signal in each sequence of n successive data signals responsive to the clock delay data received by the programmable clock delay unit for the one data signal in the sequence; a third program unit for producing reference clock delay information at the predetermined clock rate; and a fourth program unit for calibrating each of the n programmable clock delay units to a change in the predetermined clock rate.

37. The computer usable medium of claim 36 , wherein the second program unit controls a programmable clock delay unit to receive the clock delay data corresponding to a mth data signal of successive data signals in a clock period during which the programmable clock delay unit that received the clock delay data corresponding to a (m−n+1)th data signal of the successive data signals generates the output signal for determining the recording time of the (m−n+1)th data signal.

38. The computer usable medium of claim 36 , wherein the second program unit includes a program unit that reprograms each programmable clock delay unit for the one data signal received in each sequence of successive data signals.

39. The computer usable medium of claim 36 , further comprising: a fifth program unit for selecting output signals of the n programmable clock delay units successively in each n data signal sequence to control the recording times of the successive data signals of the sequence so that the clock delay data for a mth data signal is received by one of the n programmable clock delay units while the output signal of the programmable clock delay unit that is to receive a (m+1)th data signal controls the recording time of a (m−n+1)th data signal.

40. The computer usable medium of claim 36 , wherein the first program unit includes: a program unit for obtaining clock delay information from a look up table for each data signal responsive to the pattern of adjacent data signals; and a program unit for combining the look up table clock data information for each data signal with the reference clock data information for the programmable clock delay unit to which clock delay data for the data signal is sent to form the clock delay data for the data signal.

41. The computer usable medium of claim 36 , further comprising: a fifth program unit responsive to a change in write clock rate for reprogramming the reference clock delay information of each programmable clock delay unit responsive to the change in the predetermined clock rate.