Disclosed herein is a method for forming a bit line of a flash device capable of reducing loss of an interlayer insulation film between the bit line patterns. The method includes forming a bit line metal hard-mask pattern prior to forming a bit line mask pattern, preventing an interval between the bit lines from being reduced by controlling conditions of a cleaning process prior to forming a metal film. The method obviates an additional process of removing the metal hard-mask film since the metal hard-mask film is also removed at the same time of carrying out a bit line planarization process.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for forming a bit line of a flash device, the method comprising the steps of: (a) forming a barrier film, an interlayer insulation film, and a metal hard-mask film sequentially on a semiconductor substrate, on which a bit line contact plug is formed; (b) forming a metal hard-mask film pattern for opening a bit line area corresponding to the bit line contact plug; (c) forming a bit line trench; (d) forming a bit line metal film on the entire structure including the metal hard-mask film to bury the bit line trench; and, (e) removing the bit line metal film and the metal hard mask film on the interlayer insulation film with a metal material by means of CMP, wherein the metal hard-mask film and the bit line metal film are formed using the same metal material so that the metal hard-mask film and the bit line metal film can be removed at the same time by the CMP.
2. The method of claim 1 , further comprising between steps (c) and (d), a step of cleaning the bit line trench.
3. The method of claim 2 , wherein the cleaning step comprises a dry cleaning process using plasma or a cleaning process by high-frequency sputtering.
4. The method of claim 3 , wherein the dry cleaning process is performed using a mixed gas of CF 4 and O 2 and NF 3 gas, and the cleaning process by high-frequency sputtering is performed using Ar gas.
5. The method of claim 1 , the metal hard-mask film is formed using tungsten (W) with a thickness in the range of 500 Å to 1000 Å to endure significantly as an etching barrier in the subsequent process of etching the interlayer insulation film.
6. The method of claim 1 , wherein step (b) comprises patterning the metal hard-mask film.
7. The method of claim 1 , wherein step (c) comprises etching the interlayer insulation film and the barrier film using the metal hard-mask film pattern as an etching mask.
8. The method of claim 1 , wherein step (e) comprises a planarization process.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 12, 2003
November 15, 2005
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