Patentable/Patents/US-6969666
US-6969666

Method for fabricating isolation layer in semiconductor device

PublishedNovember 29, 2005
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A method for fabricating an isolation layer in a semiconductor device is disclosed. The method comprises the steps of: forming a pad oxide film and a pad nitride film sequentially on a semiconductor substrate defining a cell region and a peripheral region; forming a trench on the semiconductor substrate by etching the pad oxide film, the pad nitride film and the substrate; forming an oxide film of side walls on a surface of the trench; depositing an amorphous silicon film on a resultant substrate inclusive of the trench; etching the amorphous silicon film so that the trench is partly filled; depositing an insulation film on a resultant substrate so that the partly filled trench is filled completely; carrying out a CMP process of the insulation film to expose the pad nitride film; and removing the pad nitride film.

Patent Claims
7 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method for fabricating a field oxide in a semiconductor device, the method comprising the steps of: forming a pad oxide film and a pad nitride film sequentially on a semiconductor substrate defining a cell region and a peripheral region; forming a trench on the semiconductor substrate by etching the pad oxide film, the pad nitride film and the substrate; forming an oxide film of side walls on a surface of the trench; depositing an amorphous silicon film on a resultant substrate inclusive of the trench; etching the amorphous silicon film so that the trench is partly filled with amorphous silicon; depositing an insulation film on a resultant substrate so that the partly filled trench is filled completely; carrying out a CMP process of the insulation film to expose the pad nitride film; and removing the pad nitride film.

2

2. The method as claimed in claim 1 , wherein the amorphous silicon film is deposited to a thickness thinner than the depth of the trench.

3

3. The method as claimed in claim 1 , wherein the amorphous silicon film is deposited thicker than half of a width of the trench in the cell region, and is deposited thinner in the peripheral region than the thickness of the amorphous silicon film deposited in the cell region.

4

4. The method as claimed in claim 3 , wherein the amorphous silicon film is deposited to a thickness more than 60 nm, when a width of the trench is 120 nm.

5

5. The method as claimed in claim 1 , wherein the etching of the amorphous silicon film is carried out to remove it to a depth just below the surface of the substrate.

6

6. The method as claimed in claim 1 , wherein the amorphous silicon film is formed in an atmosphere of a mixed gas made of SiH 4 and N 2 at a deposition temperature ranging from 500 to 600° C.

7

7. The method as claimed in claim 1 , wherein the insulation film is deposited to a thickness ranging from 300 to 5000 â„«.

Classification Codes (CPC)

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Patent Metadata

Filing Date

November 7, 2003

Publication Date

November 29, 2005

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