Semiconductor memory device and electric device with the same

1. A semiconductor memory device comprising: a plurality of cell array blocks in each of which a plurality of memory cells are arranged; address decode circuits for selecting memory cells in said cell array blocks; sense amplifier circuits for reading cell data of said cell array blocks; and a busy signal generation circuit for generating a busy signal to the chip external, wherein in a first read cycle selecting a first area in a first cell array block, cell data read operations for said first area of said first cell array block and a second area of a second cell array block are simultaneously executed, while said busy signal generation circuit generates a true busy signal, and then a read data output operation is executed for outputting the read out data of said first area held in said sense amplifier circuits to the chip external, and in a second read cycle selecting said second area in said second cell array block, after said busy signal generation circuit has output a dummy busy signal shorter in time length than said true busy signal without executing cell data read operation, a read data output operation is executed for outputting the read out data of said second area held in said sense amplifier circuits to the chip external.

2. A semiconductor memory device comprising: a plurality of cell array blocks arranged as being physically independent of each other and assigned with the same page addresses, in each of which a plurality of memory cells are arranged; address decode circuits disposed for the respective cell array blocks for selecting memory cells in said cell array blocks; sense amplifier circuits disposed for the respective cell array blocks for reading cell data of said cell array blocks; and a controller for controlling data read and write operations, wherein in a first read cycle selecting a page of a first cell array block, cell data read operations for the same pages of said plurality of cell array blocks are executed at a time, and then a read data output operation is executed for outputting the read out data held in said sense amplifier circuit in correspondence with said first cell array block to the chip external, and in a second read cycle successively selecting the same page of a second cell array block, a read data output operation is executed for outputting the read out data held in said sense amplifier circuit in correspondence with said second cell array block to the chip external without cell data read operation.

3. The semiconductor memory device according to claim 2 , further comprising a busy signal generation circuit for generating a true busy signal to the chip external while a cell data read operation is performed, and wherein in said second read cycle, after said busy signal generation circuit has generated a dummy busy signal shorter in time length than said true busy signal, said read data output operation is executed.

4. The semiconductor memory device according to claim 2 , further comprising: an address transfer circuit for transferring input address data to the respective address decode circuits, and holding the address data until the following read cycle; an address latch circuit for holding address bit data corresponding to a page address in the input address data in response to a timing signal; and an address matching detector circuit for detecting whether the bit data held at said address latch circuit coincide with bit data corresponding to a page address in input address data in the following read cycle or not, wherein the read operation of said second read cycle is controlled by a detected output of said address matching circuit.

5. The semiconductor memory device according to claim 4 , wherein whether said busy signal circuit outputs said true busy signal or said dummy busy signal is determined by a detected output of said address matching circuit.

6. The semiconductor memory device according to claim 1 , wherein each said cell array block comprises electrically rewritable and non-volatile memory cells arranged therein.

7. The semiconductor memory device according to claim 6 , wherein each said cell array block comprises: a plurality of word lines; a plurality of bit lines disposed to intersect said word lines; and a plurality of NAND cell units each having a cell string with a plurality of memory cells connected in series, control gates thereof being connected to different word lines, a first select gate transistor disposed between one end of said cell string and a corresponding bit line with a gate thereof being connected a first select gate line disposed in parallel with said word lines, and a second select gate transistor disposed between the other end of said cell string and a common source line with a gate thereof being connected to a second select gate line disposed in parallel with said word lines, wherein a group of memory cells arranged along each said word line constitutes one page which serves as a unit of data read and data write.

8. The semiconductor memory device according to claim 2 , wherein each said cell array block comprises electrically rewritable and non-volatile memory cells arranged therein.

9. The semiconductor memory device according to claim 8 , wherein each said cell array block comprises: a plurality of word lines; a plurality of bit lines disposed to intersect said word lines; and a plurality of NAND cell units each having a cell string with a plurality of memory cells connected in series, control gates thereof being connected to different word lines, a first select gate transistor disposed between one end of said cell string and a corresponding bit line with a gate thereof being connected a first select gate line disposed in parallel with said word lines, and a second select gate transistor disposed between the other end of said cell string and a common source line with a gate thereof being connected to a second select gate line disposed in parallel with said word lines, and wherein a group of memory cells arranged along each said word line constitutes one page which serves as a unit of data read and data write.

10. A semiconductor memory device comprising: a plurality of cell array blocks arranged as being physically independent each other and assigned with the same page addresses, in each of which a plurality of electrically rewritable and non-volatile memory cells are arranged; address decode circuits disposed for the respective cell array blocks as being possible to select memory cells of the same page in the entire cell array blocks; sense amplifier circuits disposed for the respective cell array blocks for reading cell data of selected pages in said cell array blocks; and a controller for executing, in a first read cycle selecting a page of a first cell array block cell, data read operations for the same pages of the entire cell array blocks and a read data output operation for outputting the read out data held in said sense amplifier circuit in correspondence with said first cell array block to the chip external, and for executing, in a second read cycle successively selecting the same page of a second cell array block, a read data output operation for outputting the read out data held in said sense amplifier circuit in correspondence with said second cell array block to the chip external without cell data read operation; and a busy signal generation circuit for generating a true busy signal to the chip external while cell data read operation is performed in said first read cycle, and generating a dummy busy signal shorter in time length than said true busy signal before said read data output operation in said second read cycle.

11. The semiconductor memory device according to claim 10 , further comprising: an address transfer circuit for transferring input address data to the respective address decode circuits, and holding the address data until the following read cycle; an address latch circuit for latching bit data corresponding to a page address in the input address data in response to a timing signal; and an address matching detector circuit for detecting whether the bit data held at said address latch circuit coincide with bit data corresponding to a page address in input address data in the following read cycle or not.

12. The semiconductor memory device according to claim 11 , wherein said busy signal circuit outputs said dummy busy signal in response to detected outputs of said address matching circuits.

13. The semiconductor memory device according to claim 10 , wherein each said cell array block comprises: a plurality of word lines; a plurality of bit lines disposed to intersect said word lines; and a plurality of NAND cell units each having a cell string with a plurality of memory cells connected in series, control gates thereof being connected to different word lines, a first select gate transistor disposed between one end of said cell string and a corresponding bit line with a gate thereof being connected a first select gate line disposed in parallel with said word lines, and a second select gate transistor disposed between the other end of said cell string and a common source line with a gate thereof being connected to a second select gate line disposed in parallel with said word lines, and wherein a group of memory cells arranged along each said word line constitutes one page which serves as a unit of data read and data write.

14. An electric card equipped with a semiconductor memory device defined in claim 1 .

15. An electric card equipped with a semiconductor memory device defined in claim 2 .

16. An electric card equipped with a semiconductor memory device defined in claim 10 .

17. An electric device comprising: a card interface; a card slot connected to said card interface; and an electric card defined in claim 14 and electrically connectable to said card slot.

18. An electric device comprising: a card interface; a card slot connected to said card interface; and an electric card defined in claim 15 and electrically connectable to said card slot.

19. An electric device comprising: a card interface; a card slot connected to said card interface; and an electric card defined in claim 16 and electrically connectable to said card slot.

20. The electric device according to claim 19 , wherein said electric device is a digital still camera.