Self-test instructions are loaded from a tester into a configuration array of a memory device, and then a control circuit of the memory device sequentially reads and executes the self-test instructions while the tester is in an idle state. Data patterns are written to a main memory array of the memory device the internal self-test process. The control circuit includes a comparator for detecting defective memory cells by comparing data values read from the main array with the data pattern previously written into the main memory array. A BIN counter identifies the currently-executed self-test instruction, and is read and transmitted to the tester when an error is detected.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A non-volatile memory device comprising: a plurality of non-volatile memory cells including a first array for storing self-test instructions and a second array for storing data values; a control circuit including a command register for receiving the self-test instructions from the first array during a first operating phase, and a comparator circuit for detecting defective non-volatile memory cells in the second array by comparing the data values with predefined values during a second operating phase; an output controller for registering the self-test instructions read from the first array during the first operating phase; and a data bus connected between the output controller and the control circuit for transmitting the self-test instructions to the command register during the first operating phase.
2. The non-volatile memory device according to claim 1 , further comprising a data input buffer connected to the data bus and controlled by the control circuit such that data values received by the data input buffer are selectively passed to the command register.
3. A method for performing wafer sort testing on a non-volatile memory device using a tester, the non-volatile memory device including a first array of non-volatile memory cells, a second array of non-volatile memory cells, and a control circuit, the method comprising: storing a series of self-test instructions transmitted from the tester in the first array of the non-volatile memory device, the series of self-test instructions including a first instruction and a second instruction; reading the first instruction from the first array and transferring the first instruction to a command register of the control circuit, wherein the first instruction includes a pre-determined data pattern; writing the predetermined data pattern to a second array of non-volatile memory cells in accordance with the first instruction stored in the command register; and storing a first address code transmitted from the tester, wherein reading the first instruction includes transmitting the first address code to an addressing circuit, whereby the addressing circuit accesses and reads the first instruction from the first array.
4. The method according to claim 3 , wherein writing the predetermined data pattern to the second array comprises transmitting control signals from the control circuit to the addressing circuit that cause the addressing circuit to sequentially access each of the non-volatile memory cells of the second array.
5. The method according to claim 4 , wherein writing the predetermined data pattern further comprises transmitting the predetermined data pattern to the addressing circuit such that the predetermined data pattern is repeatedly written into the sequentially accessed non-volatile memory cells.
6. A method for performing wafer sort testing on a non-volatile memory device using a tester, the non-volatile memory device including a first array of non-volatile memory cells, a second array of non-volatile memory cells, and a control circuit, the method comprising: storing a series of self-test instructions transmitted from the tester in the first array of the non-volatile memory device, the series of self-test instructions including a first instruction and a second instruction; reading the first instruction from the first array and transferring the first instruction to a command register of the control circuit, wherein the first instruction includes a predetermined data pattern; writing the predetermined data pattern to a second array of non-volatile memory cells in accordance with the first instruction stored in the command register; transferring the second instruction from the first array to the command register of the control circuit, the second instruction including a predetermined data pattern; and reading data values from the second array of non-volatile memory cells in accordance with the second instruction; and comparing the data values read from the second array with the predetermined data pattern stored in the command register.
7. A method for performing wafer sort testing on a non-volatile memory device using a tester, the non-volatile memory device including a first array of non-volatile memory cells, a second array of non-volatile memory cells, and a control circuit, the method comprising: storing a series of self-test instructions transmitted from the tester in the first array of the non-volatile memory device, the series of self-test instructions including a first instruction and a second instruction; reading the first instruction from the first array and transferring the first instruction to a command register of the control circuit, wherein the first instruction includes a predetermined data pattern; and writing the predetermined data pattern to a second array of non-volatile memory cells in accordance with the first instruction stored in the command register, wherein storing the series of self-test instructions comprises writing the series of self-test instructions into sequentially addressed non-volatile memory cells of the first array, wherein the method further comprises storing a first address code transmitted from the tester in a counter, wherein reading the first instruction includes transmitting the first address code from the counter to an addressing circuit, whereby the addressing circuit accesses and reads the first self-test instruction from the first array, and wherein reading the second instruction includes incrementing the counter to generate a second address code, and transmitting the second address code from the counter to the addressing circuit.
8. A method for performing wafer sort testing on a non-volatile memory device using a tester, the non-volatile memory device including a first array of non-volatile memory cells, a second array of non-volatile memory cells, and a control circuit, the method comprising: storing a series of self-test instructions transmitted from the tester in the first array of the non-volatile memory device, the series of self-test instructions including a first instruction and a second instruction; reading the first instruction from the first array and transferring the first instruction to a command register of the control circuit, wherein the first instruction includes a predetermined data pattern; writing the predetermined data pattern to a second array of non-volatile memory cells in accordance with the first instruction stored in the command register; and storing a start self-test command transmitted from the tester in the command register, wherein the first instruction is read from the first array in response to the stored start self-test command.
9. A method for performing wafer sort testing on a non-volatile memory device using a tester, the non-volatile memory device including a first array of non-volatile memory cells, a second array of non-volatile memory cells, and a control circuit, the method comprising: storing a self-test instruction transmitted from the tester in the first array of the non-volatile memory device; reading the self-test instruction from the first array and transferring the self-test instruction to a command register of the control circuit, wherein the self-test instruction includes a predetermined data pattern; reading data values from the second array of non-volatile memory cells in accordance with the self-test instruction; and comparing the data values read from the second array with the predetermined data pattern; and storing an address code transmitted from the tester, wherein reading the self-test instruction includes transmitting the address code to an addressing circuit, whereby the addressing circuit accesses and reads the self-test instruction from the first array.
10. The method according to claim 9 , wherein reading the data values from the second array comprises transmitting control signals from the control circuit to the addressing circuit that cause the addressing circuit to sequentially access each non-volatile memory cell of the second array.
11. The method according to claim 10 , wherein comparing the data values read from the second array with the predetermined data pattern further comprises transmitting the data values and the predetermined data pattern to a comparator.
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August 16, 2001
December 27, 2005
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