A semiconductor chip package includes a semiconductor chip having a through hole extending there through from an active first surface to an inactive second surface. A first conductive pad at least partially surrounds the through hole on the active first surface of the semiconductor chip. The package also includes a printed circuit board having a first surface attached to the inactive second surface of the semiconductor chip, and a second conductive pad aligned with the through hole of the semiconductor chip. A conductive material fills the through hole and contacts the first and second conductive pads.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor chip package, comprising: a semiconductor chip which includes a through hole extending there through from an active first surface to an inactive second surface; a first conductive pad which at least partially surrounds the through hole on the active first surface of the semiconductor chip; a printed circuit board which includes a first surface attached to the inactive second surface of the semiconductor chip, and which further includes a second conductive pad aligned with the through hole of the semiconductor chip; and a conductive material which fills the through hole and directly contacts the first and second conductive pads.
2. A semiconductor chip package as claimed in claim 1 , wherein the conductive material comprises solder.
3. A semiconductor chip package as claimed in claim 2 , wherein the solder forms a solder bump over the active first surface of the semiconductor chip.
4. A semiconductor chip package as claimed in claim 1 , wherein the printed circuit board includes an aperture aligned below the second conductive pad opposite the through hole.
5. A semiconductor chip package as claimed in claim 4 , further comprising an electrode which is electrically connected to the second conductive pad and which protrudes through the aperture in the printed circuit board.
6. A semiconductor chip package as claimed in claim 5 , wherein the electrode is a solder ball.
7. A semiconductor chip package as claimed in claim 1 , further comprising an electrode which is electrically connected the second conductive pad and which is attached to a second surface of the printed circuit board opposite the first surface of the printed circuit board.
8. A semiconductor chip package as claimed in claim 7 , wherein the electrode is a solder ball.
9. A semiconductor chip package as claimed in claim 1 , further comprising an insulating layer located on sidewalls of the through hole of the semiconductor chip.
10. A semiconductor chip package as claimed in claim 1 , further comprising an adhesive layer interposed between the inactive second surface of the semiconductor chip and the first surface of the printed circuit board.
11. A semiconductor chip package as claimed in claim 1 , further comprising an anisotropic conductive film interposed between the inactive second surface of the semiconductor chip and the first surface of the printed circuit board.
12. A semiconductor chip package as claimed in claim 1 , further comprising a protective layer covering the active first surface of the semiconductor chip.
13. A semiconductor chip package, comprising: a semiconductor chip which includes a through hole extending there through from an active first surface to an inactive second surface; a first conductive pad which at least partially surrounds the through hole on the active first surface of the semiconductor chip; a printed circuit board which includes a first surface attached to the inactive second surface of the semiconductor chip, and which further includes a second conductive pad aligned with the through hole of the semiconductor chip; and a conductive material which fills the through hole and contacts the first and second conductive pads; wherein the conductive material comprises a metal plug which protrudes into the through hole from the second conductive pad of the printed circuit board, and solder which surrounds the metal plug.
14. A semiconductor chip package as claimed in claim 13 , wherein the solder forms a solder bump over the active first surface of the semiconductor chip.
15. A semiconductor multi-package stack, comprising: a plurality of stacked semiconductor chip packages, each chip package comprising (a) a semiconductor chip which includes a through hole extending there through from an active first surface to an inactive second surface, (b) a first conductive pad which at least partially surrounds the through hole on the active first surface of the semiconductor chip, (c) a printed circuit board which includes a first surface attached to the second surface of the semiconductor chip, and a second conductive pad which is aligned with the through hole of the semiconductor chip, and (d) a conductive material which fills the through hole and contacts the first and second conductive pads.
16. A semiconductor multi-package stack as claimed in claim 15 , wherein the semiconductor chip packages are stacked such that the conductive material of a lower chip package contacts the printed circuit board of an adjacent upper chip package.
17. A semiconductor multi-package stack as claimed in claim 16 , wherein the conductive material of each semiconductor chip package comprises solder.
18. A semiconductor multi-package stack as claimed in claim 17 , wherein the solder forms a solder bump over the active first surface of the semiconductor chip of each semiconductor chip package.
19. A semiconductor multi-package stack as claimed in claim 16 , wherein the printed circuit board of each semiconductor chip package includes an aperture aligned below the second conductive pad opposite the through hole, and wherein the conductive material of the lower chip package contacts the second conductive pad of the printed circuit board of the adjacent upper chip package through the aperture of the adjacent upper chip package.
20. A semiconductor multi-package stack as claimed in claim 16 , further comprising an electrode which is electrically connected to the second conductive pad a lowermost semiconductor chip package and which protrudes through the aperture in the printed circuit board of the lowermost semiconductor chip package.
21. A semiconductor multi-package stack as claimed in claim 16 , wherein the electrode is a solder ball.
22. A semiconductor multi-package stack as claimed in claim 16 , further comprising an electrode which is electrically connected the second conductive pad of the lowermost semiconductor chip package of the and which is attached to a second surface of the printed circuit board opposite the first surface of the printed circuit board.
23. A semiconductor multi-package stack as claimed in claim 22 , wherein the electrode is a solder ball.
24. A semiconductor chip package as claimed in claim 16 , further comprising an insulating layer located on sidewalls of the through hole of the semiconductor chip of each semiconductor chip package.
25. A semiconductor chip package as claimed in claim 16 , further comprising an adhesive layer interposed between the inactive second surface of the semiconductor chip and the first surface of the printed circuit board of each semiconductor chip package.
26. A semiconductor chip package as claimed in claim 16 , further comprising an anisotropic conductive film interposed between the inactive second surface of the semiconductor chip and the first surface of the printed circuit board of each semiconductor chip package.
27. A semiconductor chip package as claimed in claim 16 , further comprising a protective layer covering the active first surface of the semiconductor chip of an uppermost semiconductor chip package.
28. A semiconductor multi-package stack as claimed in claim 15 , wherein the semiconductor chip packages are stacked such that the conductive material of an upper chip package contacts the printed circuit board of an adjacent lower chip package.
29. A semiconductor multi-package stack, comprising a plurality of stacked semiconductor chip packages, each chip package comprising (a) a semiconductor chip which includes a through hole extending there through from an active first surface to an inactive second surface, (b) a first conductive pad which at least partially surrounds the through hole on the active first surface of the semiconductor chip, (c) a printed circuit board which includes a first surface attached to the second surface of the semiconductor chip, and a second conductive pad which is aligned with the through hole of the semiconductor chip, and (d) a conductive material which fills the through hole and contacts the first and second conductive pads; wherein the semiconductor chip packages are stacked such that the conductive material of a lower chip package contacts the printed circuit board of an adjacent upper chip package, and wherein the conductive material of each semiconductor chip package comprises a metal plug which protrudes into the through hole from the second conductive pad of the printed circuit board, and solder which surrounds the metal plug.
30. A semiconductor multi-package stack as claimed in claim 29 , wherein the solder forms a solder bump over the active first surface of the semiconductor chip of each semiconductor chip package.
31. A semiconductor multi-package stack, comprising a plurality of stacked semiconductor chip packages, each chip package comprising (a) a semiconductor chip which includes a through hole extending there through from an active first surface to an inactive second surface, (b) a first conductive pad which at least partially surrounds the through hole on the active first surface of the semiconductor chip, (c) a printed circuit board which includes a first surface attached to the second surface of the semiconductor chip, and a second conductive pad which is aligned with the through hole of the semiconductor chip, and (d) a conductive material which fills the through hole and contacts the first and second conductive pads; wherein the semiconductor chip packages are stacked such that the conductive material of an upper chip package contacts the printed circuit board of an adjacent lower chip package; and further comprising an external printed circuit board having a first conductive pad formed on a first surface and a second conductive pad formed on an opposite second surface, and further having an external electrode attached to the second conductive pad, wherein the conductive material of the bottommost semiconductor chip package is attached to the first conductive pad of the external printed circuit board, and wherein the first and second conductive pads of the external printed circuit board are electrically connected.
32. A semiconductor multi-package stack as claimed in claim 31 , wherein the external electrode is a solder ball.
33. A semiconductor chip package, comprising: a semiconductor chip which includes a through hole extending there through from an active first surface to an inactive second surface; a first conductive pad which at least partially surrounds the through hole on the active first surface of the semiconductor chip; a printed circuit board which includes a first surface attached to the inactive second surface of the semiconductor chip, and which further includes a second conductive pad aligned with the through hole of the semiconductor chip; and a conductive material which fills the through hole and contacts the first and second conductive pads; wherein the printed circuit board includes an aperture aligned below the second conductive pad opposite the through hole.
34. A semiconductor chip package as claimed in claim 33 , further comprising an electrode which is electrically connected to the second conductive pad and which protrudes through the aperture in the printed circuit board.
35. A semiconductor chip package as claimed in claim 34 , wherein the electrode is a solder ball.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 22, 2003
January 3, 2006
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